PIC16F627A-I/SO Microchip Technology, PIC16F627A-I/SO Datasheet - Page 110

• Manufacturer Part Number: PIC16F627A-I/SO
• Description: IC MCU FLASH 1KX14 EEPROM 18SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F627A-I/SO

• Program Memory Type: FLASH
• Program Memory Size: 1.75KB (1K x 14)
• Package / Case: 18-SOIC (7.5mm Width)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 16
• Eeprom Size: 128 x 8
• Ram Size: 224 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 224 B
• Interface Type: SCI/USART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 3
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163014, DM164120-4
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT18SO-1 - SOCKET TRANSITION 18SOIC 300MILI3DBF648 - BOARD DAUGHTER ICEPIC3AC162053 - HEADER INTERFACE ICD,ICD2 18DIPAC164010 - MODULE SKT PROMATEII DIP/SOIC
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC16F627A/628A/648A
14.8.1
The device can wake-up from Sleep through one of the
following events:
1.
2.
3.
The first event will cause a device Reset. The two latter
events are considered a continuation of program
execution. The TO and PD bits in the Status Register
can be used to determine the cause of device Reset.
PD bit, which is set on power-up is cleared when Sleep
is invoked. TO bit is cleared if WDT wake-up occurred.
FIGURE 14-17:
14.9
With the Code Protect bit is cleared (Code Protect
enabled) the contents of the program memory locations
are read out as “00”. See Programing Specification,
DS41196, for details.
DS40044B-page 108
Note
OSC1
CLKOUT
INT pin
INTF flag
(INTCON<1>)
GIE bit
(INTCON<7>)
INSTRUCTION FLOW
Instruction
Fetched
Executed
Instruction
Note:
External Reset input on MCLR pin
Watchdog Timer wake-up (if WDT was enabled)
Interrupt from RB0/INT pin, RB Port change, or
any Peripheral Interrupt.
1: XT, HS or LP Oscillator mode assumed.
2: T
3: GIE = ‘1’ assumed. In this case after wake-up, the processor jumps to the interrupt routine. If GIE = ‘0’, execution will continue
4: CLKOUT is not available in these Osc modes, but shown here for timing reference.
PC
(4)
Code Protection
in-line.
Only a Bulk Erase function can set the CP
and CPD bits by turning off the code
protection. The entire data EEPROM and
Flash program memory will be erased to
turn the code protection off.
WAKE-UP FROM SLEEP
OST
Inst(PC) = Sleep
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
Inst(PC - 1)
= 1024T
PC
OSC
WAKE-UP FROM SLEEP THROUGH INTERRUPT
(drawing not to scale). Approximately 1 s delay will be there for RC Osc mode.
Inst(PC + 1)
Sleep
PC+1
Processor in
Sleep
PC+2
Preliminary
Tost
(2)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Interrupt Latency
Inst(PC + 2)
Inst(PC + 1)
(Note 2)
When the
next instruction (PC + 1) is pre-fetched. For the device
to wake-up through an interrupt event, the correspond-
ing interrupt enable bit must be set (enabled). Wake-up
is regardless of the state of the GIE bit. If the GIE bit is
clear (disabled), the device continues execution at the
instruction after the
set (enabled), the device executes the instruction after
the
rupt address (0004h). In cases where the execution of
the instruction following
user should have an
The WDT is cleared when the device wakes up from
Sleep, regardless of the source of wake-up.
14.10 User ID Locations
Four memory locations (2000h-2003h) are designated
as user ID locations where the user can store
checksum or other code-identification numbers. These
locations are not accessible during normal execution
but are readable and writable during program/verify.
Only the Least Significant 4 bits of the user ID locations
are used.
PC+2
Note:
SLEEP
Dummy cycle
SLEEP
If the global interrupts are disabled (GIE is
cleared), but any interrupt source has both
its interrupt enable bit and the correspond-
ing interrupt flag bits set, the device will not
enter Sleep. The SLEEP instruction is
executed as a NOP instruction.
instruction and then branches to the inter-
PC + 2
instruction is being executed, the
SLEEP
NOP
 2004 Microchip Technology Inc.
SLEEP
Inst(0004h)
Dummy cycle
after the
0004h
instruction. If the GIE bit is
is not desirable, the
SLEEP
Inst(0005h)
Inst(0004h)
0005h
instruction.