PIC18F26K20-E/SP Microchip Technology, PIC18F26K20-E/SP Datasheet - Page 126
![IC PIC MCU FLASH 32KX16 28-DIP](/photos/6/59/65908/150-28-dip_sml.jpg)
PIC18F26K20-E/SP
Manufacturer Part Number
PIC18F26K20-E/SP
Description
IC PIC MCU FLASH 32KX16 28-DIP
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.PIC18F25K20T-ISS.pdf
(42 pages)
2.PIC18F25K20T-ISS.pdf
(456 pages)
3.PIC18F26K20-ISS.pdf
(6 pages)
4.PIC18F26K20-ISS.pdf
(10 pages)
5.PIC18F26K20-ISO.pdf
(430 pages)
Specifications of PIC18F26K20-E/SP
Program Memory Type
FLASH
Program Memory Size
64KB (32K x 16)
Package / Case
28-DIP (0.300", 7.62mm)
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
24
Eeprom Size
1K x 8
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3936 B
Interface Type
CCP, ECCP, EUSART, I2C, MSSP, SPI
Maximum Clock Frequency
64 MHz
Number Of Programmable I/os
25
Number Of Timers
4
Maximum Operating Temperature
+ 125 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 11 Channel
Package
28SPDIP
Device Core
PIC
Family Name
PIC18
Maximum Speed
64 MHz
Operating Supply Voltage
2.5|3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164112 - VOLTAGE LIMITER MPLAB ICD2 VPP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
- PIC18F25K20T-ISS PDF datasheet
- PIC18F25K20T-ISS PDF datasheet #2
- PIC18F26K20-ISS PDF datasheet #3
- PIC18F26K20-ISS PDF datasheet #4
- PIC18F26K20-ISO PDF datasheet #5
- Current page: 126 of 430
- Download datasheet (7Mb)
PIC18F2XK20/4XK20
TABLE 10-3:
TABLE 10-4:
DS41303D-page 124
PORTB
LATB
TRISB
WPUB
IOCB
SLRCON
INTCON
INTCON2
INTCON3
ANSELH
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTB.
Note 1:
RB6/KBI2/PGC
RB7/KBI3/PGD
Legend:
Note 1:
Name
2:
3:
Pin
Not implemented on PIC18F2XK20 devices.
DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output;
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Configuration on POR is determined by the PBADEN Configuration bit. Pins are configured as analog inputs by default
when PBADEN is set and digital inputs when PBADEN is cleared.
Alternate assignment for CCP2 when the CCP2MX Configuration bit is ‘0’. Default assignment is RC1.
All other pin functions are disabled when ICSP or ICD are enabled.
PORTB Data Latch Register (Read and Write to Data Latch)
PORTB Data Direction Control Register
GIE/GIEH PEIE/GIEL TMR0IE
WPUB7
INT2IP
IOCB7
RBPU
Bit 7
PORTB I/O SUMMARY (CONTINUED)
SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
RB7
—
—
Function
KBI2
PGC
KBI3
PGD
RB6
RB7
INTEDG0 INTEDG1 INTEDG2
WPUB6
IOCB6
INT1IP
Bit 6
RB6
Setting
—
—
TRIS
0
1
1
x
0
1
1
x
x
WPUB5
I/O
IOCB5
O
O
O
I
I
I
I
I
I
Bit 5
RB5
—
—
—
Type
DIG
TTL
TTL
DIG
TTL
TTL
DIG
I/O
ST
ST
Preliminary
SLRE
WPUB4
INT0IE
INT2IE
ANS12
IOCB4
Bit 4
RB4
LATB<6> data output.
PORTB<6> data input; Programmable weak pull-up.
Interrupt-on-pin change.
Serial execution (ICSP) clock input for ICSP and ICD operation.
LATB<7> data output.
PORTB<7> data input; Programmable weak pull-up.
Interrupt-on-pin change.
Serial execution data output for ICSP and ICD operation.
Serial execution data input for ICSP and ICD operation.
(1)
SLRD
WPUB3
INT1IE
ANS11
RBIE
Bit 3
RB3
—
—
(1)
TMR0IF
TMR0IP
WPUB2
ANS10
SLRC
Bit 2
RB2
—
—
Description
WPUB1
INT0IF
INT2IF
SLRB
ANS9
© 2008 Microchip Technology Inc.
Bit 1
RB1
—
—
WPUB0
INT1IF
SLRA
ANS8
RBIF
RBIP
Bit 0
RB0
—
(3)
(3)
on page
Values
Reset
(3)
60
60
60
60
60
61
57
57
57
60
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