PIC18F26K20-E/SP Microchip Technology, PIC18F26K20-E/SP Datasheet - Page 326
![IC PIC MCU FLASH 32KX16 28-DIP](/photos/6/59/65908/150-28-dip_sml.jpg)
PIC18F26K20-E/SP
Manufacturer Part Number
PIC18F26K20-E/SP
Description
IC PIC MCU FLASH 32KX16 28-DIP
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.PIC18F25K20T-ISS.pdf
(42 pages)
2.PIC18F25K20T-ISS.pdf
(456 pages)
3.PIC18F26K20-ISS.pdf
(6 pages)
4.PIC18F26K20-ISS.pdf
(10 pages)
5.PIC18F26K20-ISO.pdf
(430 pages)
Specifications of PIC18F26K20-E/SP
Program Memory Type
FLASH
Program Memory Size
64KB (32K x 16)
Package / Case
28-DIP (0.300", 7.62mm)
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
24
Eeprom Size
1K x 8
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3936 B
Interface Type
CCP, ECCP, EUSART, I2C, MSSP, SPI
Maximum Clock Frequency
64 MHz
Number Of Programmable I/os
25
Number Of Timers
4
Maximum Operating Temperature
+ 125 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 11 Channel
Package
28SPDIP
Device Core
PIC
Family Name
PIC18
Maximum Speed
64 MHz
Operating Supply Voltage
2.5|3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164112 - VOLTAGE LIMITER MPLAB ICD2 VPP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
- PIC18F25K20T-ISS PDF datasheet
- PIC18F25K20T-ISS PDF datasheet #2
- PIC18F26K20-ISS PDF datasheet #3
- PIC18F26K20-ISS PDF datasheet #4
- PIC18F26K20-ISO PDF datasheet #5
- Current page: 326 of 430
- Download datasheet (7Mb)
PIC18F2XK20/4XK20
BTFSC
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
DS41303D-page 324
Q Cycle Activity:
If skip:
If skip and followed by 2-word instruction:
Before Instruction
After Instruction
operation
operation
operation
Decode
PC
If FLAG<1>
If FLAG<1>
Q1
Q1
No
Q1
No
No
PC
PC
Bit Test File, Skip if Clear
BTFSC f, b {,a}
0 ≤ f ≤ 255
0 ≤ b ≤ 7
a ∈ [0,1]
skip if (f<b>) = 0
None
If bit ‘b’ in register ‘f’ is ‘0’, then the next
instruction is skipped. If bit ‘b’ is ‘0’, then
the next instruction fetched during the
current instruction execution is discarded
and a
this a two-cycle instruction.
If ‘a’ is ‘0’, the Access Bank is selected. If
‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates in
Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh).
See Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
1
1(2)
Note: 3 cycles if skip and followed
HERE
FALSE
TRUE
register ‘f’
operation
operation
operation
1011
Read
=
=
=
=
=
Q2
Q2
Q2
No
No
No
NOP
by a 2-word instruction.
address (HERE)
0;
address (TRUE)
1;
address (FALSE)
BTFSC
:
:
is executed instead, making
bbba
operation
operation
operation
Process
Data
Q3
Q3
Q3
No
No
No
FLAG, 1, 0
ffff
operation
operation
operation
operation
Q4
No
Q4
No
Q4
No
No
ffff
Preliminary
BTFSS
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
If skip:
If skip and followed by 2-word instruction:
Before Instruction
After Instruction
operation
operation
operation
Decode
PC
If FLAG<1>
If FLAG<1>
Q1
Q1
No
Q1
No
No
PC
PC
Bit Test File, Skip if Set
BTFSS f, b {,a}
0 ≤ f ≤ 255
0 ≤ b < 7
a ∈ [0,1]
skip if (f<b>) = 1
None
instruction is skipped. If bit ‘b’ is ‘1’, then
the next instruction fetched during the
current instruction execution is discarded
and a
this a two-cycle instruction.
If ‘a’ is ‘0’, the Access Bank is selected. If
‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh).
See Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
1
1(2)
Note:
If bit ‘b’ in register ‘f’ is ‘1’, then the next
register ‘f’
operation
operation
operation
HERE
FALSE
TRUE
1010
Read
Q2
Q2
No
Q2
No
No
=
=
=
=
=
NOP
© 2008 Microchip Technology Inc.
3 cycles if skip and followed
by a 2-word instruction.
address (HERE)
0;
address (FALSE)
1;
address (TRUE)
is executed instead, making
BTFSS
:
:
bbba
operation
operation
operation
Process
Data
Q3
Q3
Q3
No
No
No
FLAG, 1, 0
ffff
operation
operation
operation
operation
Q4
Q4
No
Q4
No
No
No
ffff
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