ATMEGA8535L-8JU Atmel, ATMEGA8535L-8JU Datasheet - Page 42

• Manufacturer Part Number: ATMEGA8535L-8JU
• Description: MCU AVR 8K ISP FLASH MEM 44-PLCC
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA8535L-8JU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-PLCC
• Processor Series: ATMEGA8x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: 2-Wire, SPI, USART
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Cpu Family: ATmega
• Device Core: AVR
• Device Core Size: 8b
• Frequency (max): 8MHz
• Total Internal Ram Size: 512Byte
• # I/os (max): 32
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 44
• Package Type: PLCC
• For Use With: ATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRISP2 - PROGRAMMER AVR IN SYSTEMATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Watchdog Timer Control
Register – WDTCR
42
ATmega8535(L)
Table 17. WDT Configuration as a Function of the Fuse Settings of S8538C and
WDTON
Figure 21. Watchdog Timer
• Bits 7..5 – Res: Reserved Bits
These bits are reserved bits in the ATmega8535 and will always read as zero.
• Bit 4 – WDCE: Watchdog Change Enable
This bit must be set when the WDE bit is written to logic zero. Otherwise, the Watchdog
will not be disabled. Once written to one, hardware will clear this bit after four clock
cycles. Refer to the description of the WDE bit for a Watchdog disable procedure. In
Safety Level 1 and 2, this bit must also be set when changing the prescaler bits. See
“Timed Sequences for Changing the Configuration of the Watchdog Timer” on page 45.
• Bit 3 – WDE: Watchdog Enable
When the WDE is written to logic one, the Watchdog Timer is enabled, and if the WDE is
written to logic zero, the Watchdog Timer function is disabled. WDE can only be cleared
Bit
Read/Write
Initial Value
S8535C
Unprogrammed
Unprogrammed
Programmed
Programmed
R
7
–
0
WDTON
Unprogrammed
Programmed
Unprogrammed
Programmed
OSCILLATOR
WATCHDOG
R
6
–
0
R
5
–
0
Safety
Level
1
2
0
2
WDCE
R/W
4
0
WDT Initial
State
Disabled
Enabled
Disabled
Enabled
WDE
R/W
3
0
WDP2
R/W
2
0
How to Disable
the WDT
Timed
sequence
Always enabled
Timed
sequence
Always enabled
WDP1
R/W
1
0
WDP0
R/W
0
0
2502K–AVR–10/06
How to
Change
Time-out
Timed
sequence
Timed
sequence
No
restriction
Timed
sequence
WDTCR