ATMEGA8535L-8JU Atmel, ATMEGA8535L-8JU Datasheet - Page 45

• Manufacturer Part Number: ATMEGA8535L-8JU
• Description: MCU AVR 8K ISP FLASH MEM 44-PLCC
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA8535L-8JU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-PLCC
• Processor Series: ATMEGA8x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: 2-Wire, SPI, USART
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Cpu Family: ATmega
• Device Core: AVR
• Device Core Size: 8b
• Frequency (max): 8MHz
• Total Internal Ram Size: 512Byte
• # I/os (max): 32
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 44
• Package Type: PLCC
• For Use With: ATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRISP2 - PROGRAMMER AVR IN SYSTEMATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Timed Sequences for
Changing the
Configuration of the
Watchdog Timer
Safety Level 0
Safety Level 1
Safety Level 2
2502K–AVR–10/06
The sequence for changing the Watchdog Timer configuration differs slightly between
the three safety levels. Separate procedures are described for each level.
This mode is compatible with the Watchdog operation found in AT90S8535. The Watch-
dog Timer is initially disabled, but can be enabled by writing the WDE bit to 1 without
any restriction. The Time-out period can be changed at any time without restriction. To
disable an enabled Watchdog Timer and/or changing the Watchdog Time-out, the fol-
lowing procedure must be followed:
1. In the same operation, write a logic one to WDCE and WDE. A logic one must be
2. Within the next four clock cycles, in the same operation, write the WDE and WDP
In this mode, the Watchdog Timer is initially disabled, but can be enabled by writing the
WDE bit to 1 without any restriction. A timed sequence is needed when changing the
Watchdog Time-out period or disabling an enabled Watchdog Timer. To disable an
enabled Watchdog Timer and/or changing the Watchdog Time-out, the following proce-
dure must be followed:
1. In the same operation, write a logic one to WDCE and WDE. A logic one must be
2. Within the next four clock cycles, in the same operation, write the WDE and WDP
In this mode, the Watchdog Timer is always enabled, and the WDE bit will always read
as one. A timed sequence is needed when changing the Watchdog Time-out period. To
change the Watchdog Time-out, the following procedure must be followed:
1. In the same operation, write a logical one to WDCE and WDE. Even though the
2. Within the next four clock cycles, in the same operation, write the WDP bits as
written to WDE regardless of the previous value of the WDE bit.
bits as desired, but with the WDCE bit cleared.
written to WDE regardless of the previous value of the WDE bit.
bits as desired, but with the WDCE bit cleared.
WDE always is set, the WDE must be written to one to start the timed sequence.
desired, but with the WDCE bit cleared. The value written to the WDE bit is
irrelevant.
ATmega8535(L)
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