DSPIC33FJ64MC202-I/SP Microchip Technology, DSPIC33FJ64MC202-I/SP Datasheet - Page 157
![IC DSPIC MCU/DSP 64K 28DIP](/photos/6/59/65908/150-28-dip_sml.jpg)
DSPIC33FJ64MC202-I/SP
Manufacturer Part Number
DSPIC33FJ64MC202-I/SP
Description
IC DSPIC MCU/DSP 64K 28DIP
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheets
1.DSPIC33FJ32MC202-IMM.pdf
(14 pages)
2.DSPIC33FJ32MC302-ISO.pdf
(436 pages)
3.DSPIC33FJ64MC202-ESO.pdf
(424 pages)
Specifications of DSPIC33FJ64MC202-I/SP
Program Memory Type
FLASH
Program Memory Size
64KB (64K x 8)
Package / Case
28-DIP (0.300", 7.62mm)
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
21
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 6x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Product
DSCs
Data Bus Width
16 bit
Processor Series
DSPIC33F
Core
dsPIC
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
21
Data Ram Size
8 KB
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DV164033
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
- DSPIC33FJ32MC202-IMM PDF datasheet
- DSPIC33FJ32MC302-ISO PDF datasheet #2
- DSPIC33FJ64MC202-ESO PDF datasheet #3
- Current page: 157 of 424
- Download datasheet (6Mb)
10.0
The
dsPIC33FJ64MCX02/X04
dsPIC33FJ128MCX02/X04 devices provide the ability
to
managing clocking to the CPU and the peripherals.
In general, a lower clock frequency and a reduction
in the number of circuits being clocked constitutes
lower consumed power.
dsPIC33FJ32MC302/304,
and dsPIC33FJ128MCX02/X04 devices can manage
power consumption in four ways:
• Clock frequency
• Instruction-based Sleep and Idle modes
• Software-controlled Doze mode
• Selective peripheral control in software
Combinations of these methods can be used to
selectively tailor an application’s power consumption
while still maintaining critical application features, such
as timing-sensitive communications.
10.1
dsPIC33FJ32MC302/304,
and dsPIC33FJ128MCX02/X04 devices allow a wide
range of clock frequencies to be selected under
application control. If the system clock configuration is
not
high-precision oscillators by simply changing the
NOSC bits (OSCCON<10:8>). The process of
EXAMPLE 10-1:
© 2009 Microchip Technology Inc.
PWRSAV #SLEEP_MODE
PWRSAV #IDLE_MODE
Note 1: This data sheet summarizes the features
manage
locked,
2: Some registers and associated bits
POWER-SAVING FEATURES
Clock Frequency and Clock
Switching
of
dsPIC33FJ64MCX02/X04
dsPIC33FJ128MCX02/X04
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to “Section 9. Watchdog
Timer and Power Savings Modes”
(DS70196) of the “dsPIC33F/PIC24H
Family Reference Manual”, which is avail-
able
(www.microchip.com).
described in this section may not be avail-
able on all devices. Refer to Section 4.0
“Memory Organization” in this data
sheet for device-specific register and bit
information.
power
users
the
from
PWRSAV INSTRUCTION SYNTAX
can
consumption
the
dsPIC33FJ32MC302/304,
dsPIC33FJ32MC302/304,
dsPIC33FJ64MCX02/X04
dsPIC33FJ64MCX02/X04
; Put the device into SLEEP mode
; Put the device into IDLE mode
choose
Microchip
by
low-power
family
selectively
website
and
and
Preliminary
of
or
changing a system clock during operation, as well as
limitations to the process, are discussed in more detail
in Section 9.0 “Oscillator Configuration”.
10.2
dsPIC33FJ32MC302/304,
and dsPIC33FJ128MCX02/X04 devices have two
special power-saving modes that are entered through
the execution of a special PWRSAV instruction. Sleep
mode stops clock operation and halts all code
execution. Idle mode halts the CPU and code
execution, but allows peripheral modules to continue
operation. The assembler syntax of the PWRSAV
instruction is shown in Example 10-1.
Sleep and Idle modes can be exited as a result of an
enabled interrupt, WDT time-out or a device Reset. When
the device exits these modes, it is said to wake up.
10.2.1
The following occur in Sleep mode:
• The system clock source is shut down. If an
• The device current consumption is reduced to a
• The Fail-Safe Clock Monitor does not operate,
• The LPRC clock continues to run in Sleep mode if
• The WDT, if enabled, is automatically cleared
• Some device features or peripherals can continue
• Any peripheral that requires the system clock
The device wakes up from Sleep mode on any of the
these events:
• Any interrupt source that is individually enabled
• Any form of device Reset
• A WDT time-out
On wake-up from Sleep mode, the processor restarts
with the same clock source that was active when Sleep
mode was entered.
on-chip oscillator is used, it is turned off.
minimum, provided that no I/O pin is sourcing
current.
since the system clock source is disabled.
the WDT is enabled.
prior to entering Sleep mode.
to operate. This includes items such as the input
change notification on the I/O ports, or peripherals
that use an external clock input.
source for its operation is disabled.
Note:
Instruction-Based Power-Saving
Modes
SLEEP MODE
SLEEP_MODE and IDLE_MODE are
constants defined in the assembler
include file for the selected device.
dsPIC33FJ64MCX02/X04
DS70291D-page 157
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