DSPIC33FJ64MC202-I/SP Microchip Technology, DSPIC33FJ64MC202-I/SP Datasheet - Page 167
![IC DSPIC MCU/DSP 64K 28DIP](/photos/6/59/65908/150-28-dip_sml.jpg)
DSPIC33FJ64MC202-I/SP
Manufacturer Part Number
DSPIC33FJ64MC202-I/SP
Description
IC DSPIC MCU/DSP 64K 28DIP
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheets
1.DSPIC33FJ32MC202-IMM.pdf
(14 pages)
2.DSPIC33FJ32MC302-ISO.pdf
(436 pages)
3.DSPIC33FJ64MC202-ESO.pdf
(424 pages)
Specifications of DSPIC33FJ64MC202-I/SP
Program Memory Type
FLASH
Program Memory Size
64KB (64K x 8)
Package / Case
28-DIP (0.300", 7.62mm)
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
21
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 6x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Product
DSCs
Data Bus Width
16 bit
Processor Series
DSPIC33F
Core
dsPIC
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
21
Data Ram Size
8 KB
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DV164033
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
- DSPIC33FJ32MC202-IMM PDF datasheet
- DSPIC33FJ32MC302-ISO PDF datasheet #2
- DSPIC33FJ64MC202-ESO PDF datasheet #3
- Current page: 167 of 424
- Download datasheet (6Mb)
11.6.2.2
In contrast to inputs, the outputs of the peripheral pin
select options are mapped on the basis of the pin. In
this case, a control register associated with a particular
pin dictates the peripheral output to be mapped. The
RPORx registers are used to control output mapping.
Like the RPINRx registers, each register contains sets
of 5-bit fields, with each set associated with one RPn
pin (see Register 11-21 through Register 11-33). The
value of the bit field corresponds to one of the
peripherals, and that peripheral’s output is mapped to
the pin (see Table 11-2 and Figure 11-3).
The list of peripherals for output mapping also includes
a null value of ‘00000’
technique. This permits any given pin to remain
unconnected from the output of any of the pin
selectable peripherals.
TABLE 11-2:
© 2009 Microchip Technology Inc.
Function
C1OUT
C2OUT
UPDN1
UPDN2
U1RTS
U2RTS
SDO1
SDO2
SCK1
SCK2
NULL
U1TX
U2TX
C1TX
OC1
OC2
OC3
OC4
SS1
SS2
Output Mapping
OUTPUT SELECTION FOR REMAPPABLE PIN (RPn)
because of the mapping
RPnR<4:0>
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
10000
10010
10011
10100
10101
11010
11011
Preliminary
RPn tied to default port pin
RPn tied to Comparator1 Output
RPn tied to Comparator2 Output
RPn tied to UART1 Transmit
RPn tied to UART1 Ready To Send
RPn tied to UART2 Transmit
RPn tied to UART2 Ready To Send
RPn tied to SPI1 Data Output
RPn tied to SPI1 Clock Output
RPn tied to SPI1 Slave Select Output
RPn tied to SPI2 Data Output
RPn tied to SPI2 Clock Output
RPn tied to SPI2 Slave Select Output
RPn tied to ECAN1 Transmit
RPn tied to Output Compare 1
RPn tied to Output Compare 2
RPn tied to Output Compare 3
RPn tied to Output Compare 4
RPn tied to QEI1 direction (UPDN) status
RPn tied to QEI2 direction (UPDN) status
FIGURE 11-3:
UPDN2 Output enable
U1RTS Output enable 4
U1TX Output enable
UPDN2 Output
U1RTS Output 4
U1TX Output
default
default
Output Name
RPnR<4:0>
MULTIPLEXING OF
REMAPPABLE OUTPUT
FOR RPn
0
27
0
27
3
3
Output Enable
Output Data
DS70291D-page 167
RPn
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