DSPIC33FJ64MC202-I/SP Microchip Technology, DSPIC33FJ64MC202-I/SP Datasheet - Page 25
![IC DSPIC MCU/DSP 64K 28DIP](/photos/6/59/65908/150-28-dip_sml.jpg)
DSPIC33FJ64MC202-I/SP
Manufacturer Part Number
DSPIC33FJ64MC202-I/SP
Description
IC DSPIC MCU/DSP 64K 28DIP
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheets
1.DSPIC33FJ32MC202-IMM.pdf
(14 pages)
2.DSPIC33FJ32MC302-ISO.pdf
(436 pages)
3.DSPIC33FJ64MC202-ESO.pdf
(424 pages)
Specifications of DSPIC33FJ64MC202-I/SP
Program Memory Type
FLASH
Program Memory Size
64KB (64K x 8)
Package / Case
28-DIP (0.300", 7.62mm)
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
21
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 6x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Product
DSCs
Data Bus Width
16 bit
Processor Series
DSPIC33F
Core
dsPIC
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
21
Data Ram Size
8 KB
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DV164033
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
- DSPIC33FJ32MC202-IMM PDF datasheet
- DSPIC33FJ32MC302-ISO PDF datasheet #2
- DSPIC33FJ64MC202-ESO PDF datasheet #3
- Current page: 25 of 424
- Download datasheet (6Mb)
3.0
3.1
The
dsPIC33FJ64MCX02/X04
dsPIC33FJ128MCX02/X04 CPU module has a 16-bit
(data) modified Harvard architecture with an enhanced
instruction set, including significant support for DSP.
The CPU has a 24-bit instruction word with a variable
length opcode field. The Program Counter (PC) is
23 bits wide and addresses up to 4M x 24 bits of user
program memory space. The actual amount of program
memory implemented varies by device. A single-cycle
instruction prefetch mechanism is used to help main-
tain throughput and provides predictable execution. All
instructions execute in a single cycle, with the excep-
tion of instructions that change the program flow, the
double-word move (MOV.D) instruction and the table
instructions. Overhead-free program loop constructs
are supported using the DO and REPEAT instructions,
both of which are interruptible at any time.
The
dsPIC33FJ64MCX02/X04
dsPIC33FJ128MCX02/X04 devices have sixteen,
16-bit working registers in the programmer’s model.
Each of the working registers can serve as a data,
address or address offset register. The 16th working
register (W15) operates as a software Stack Pointer
(SP) for interrupts and calls.
© 2009 Microchip Technology Inc.
Note 1: This data sheet summarizes the features
2: Some registers and associated bits
CPU
Overview
of
dsPIC33FJ64MCX02/X04
dsPIC33FJ128MCX02/X04
devices. It is not intended to be a compre-
hensive reference source. To comple-
ment the information in this data sheet,
refer to “Section 2. CPU” (DS70204) of
the “dsPIC33F/PIC24H Family Reference
Manual”, which is available from the
Microchip website (www.microchip.com).
described in this section may not be avail-
able on all devices. Refer to Section 4.0
“Memory Organization” in this data
sheet for device-specific register and bit
information.
dsPIC33FJ32MC302/304,
dsPIC33FJ32MC302/304,
dsPIC33FJ32MC302/304,
family
and
and
and
Preliminary
of
There
dsPIC33FJ32MC302/304,
and dsPIC33FJ128MCX02/X04 devices: MCU and
DSP. These two instruction classes are seamlessly
integrated into a single CPU. The instruction set
includes many addressing modes and is designed for
optimum C compiler efficiency. For most instructions,
the
dsPIC33FJ64MCX02/X04
dsPIC33FJ128MCX02/X04 is capable of executing a
data (or program data) memory read, a working
register (data) read, a data memory write and a
program (instruction) memory read per instruction
cycle. As a result, three parameter instructions can be
supported, allowing A + B = C operations to be
executed in a single cycle.
A block diagram of the CPU is shown in Figure 3-1, and
the
dsPIC33FJ32MC302/304,
and dsPIC33FJ128MCX02/X04 is shown in Figure 3-2.
3.2
The data space can be addressed as 32K words or
64 Kbytes and is split into two blocks, referred to as X
and Y data memory. Each memory block has its own
independent Address Generation Unit (AGU). The
MCU class of instructions operates solely through the
X memory AGU, which accesses the entire memory
map as one linear data space. Certain DSP instructions
operate through the X and Y AGUs to support dual
operand reads, which splits the data address space
into two parts. The X and Y data space boundary is
device-specific.
Overhead-free circular buffers (Modulo Addressing
mode) are supported in both X and Y address spaces.
The Modulo Addressing removes the software
boundary checking overhead for DSP algorithms.
Furthermore, the X AGU circular addressing can be
used with any of the MCU class of instructions. The X
AGU also supports Bit-Reversed Addressing to greatly
simplify input or output data reordering for radix-2 FFT
algorithms.
The upper 32 Kbytes of the data space memory map
can optionally be mapped into program space at any
16K program word boundary defined by the 8-bit
Program Space Visibility Page (PSVPAG) register. The
program-to-data-space mapping feature lets any
instruction access program space as if it were data
space.
are
Data Addressing Overview
programmer’s
two
classes
dsPIC33FJ32MC302/304,
dsPIC33FJ64MCX02/X04
dsPIC33FJ64MCX02/X04
model
of
instruction
DS70291D-page 25
for
in
and
the
the
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