PIC18F2455-I/SP Microchip Technology, PIC18F2455-I/SP Datasheet - Page 239

• Manufacturer Part Number: PIC18F2455-I/SP
• Description: IC PIC MCU FLASH 12KX16 28DIP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F2455-I/SP

• Program Memory Type: FLASH
• Program Memory Size: 24KB (12K x 16)
• Package / Case: 28-DIP (0.300", 7.62mm)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 24
• Eeprom Size: 256 x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SPI/I2C/EAUSART
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 4
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DM163014, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10-ch x 10-bit
• Package: 28SPDIP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 48 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: I3-DB18F4550 - BOARD DAUGHTER ICEPIC3DM163025 - PIC DEM FULL SPEED USB DEMO BRDDVA18XP280 - DEVICE ADAPTER 18F2220 PDIP 28LD
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

20.1
The BRG is a dedicated 8-bit or 16-bit generator that
supports both the Asynchronous and Synchronous
modes of the EUSART. By default, the BRG operates
in 8-bit mode; setting the BRG16 bit (BAUDCON<3>)
selects 16-bit mode.
The SPBRGH:SPBRG register pair controls the period
of a free running timer. In Asynchronous mode, bits
BRGH (TXSTA<2>) and BRG16 (BAUDCON<3>) also
control the baud rate. In Synchronous mode, BRGH is
ignored. Table 20-1 shows the formula for computation
of the baud rate for different EUSART modes which
only apply in Master mode (internally generated clock).
Given the desired baud rate and F
integer value for the SPBRGH:SPBRG registers can be
calculated using the formulas in Table 20-1. From this,
the error in baud rate can be determined. An example
calculation is shown in Example 20-1. Typical baud
rates and error values for the various Asynchronous
modes are shown in Table 20-2. It may be advanta-
TABLE 20-1:
EXAMPLE 20-1:
TABLE 20-2:
 2004 Microchip Technology Inc.
Legend: x = Don’t care, n = value of SPBRGH:SPBRG register pair
TXSTA
RCSTA
BAUDCON
SPBRGH
SPBRG
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the BRG.
For a device with F
Desired Baud Rate
Solving for SPBRGH:SPBRG:
Calculated Baud Rate
Error
SYNC
Name
0
0
0
0
1
1
Baud Rate Generator (BRG)
Configuration Bits
EUSART Baud Rate Generator Register High Byte
EUSART Baud Rate Generator Register Low Byte
ABDOVF
CSRC
SPEN
Bit 7
BAUD RATE FORMULAS
BRG16
X
REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR
OSC
0
0
1
1
0
1
CALCULATING BAUD RATE ERROR
of 16 MHz, desired baud rate of 9600, Asynchronous mode, 8-bit BRG:
= F
= ((F
= ((16000000/9600)/64) – 1
= [25.042] = 25
= 9615
= (Calculated Baud Rate – Desired Baud Rate)/Desired Baud Rate
= (9615 – 9600)/9600 = 0.16%
= 16000000/(64 (25 + 1))
RCIDL
OSC
Bit 6
RX9
TX9
OSC
/(64 ([SPBRGH:SPBRG] + 1)
BRGH
/Desired Baud Rate)/64) – 1
0
1
0
1
x
x
OSC
SREN
TXEN
Bit 5
, the nearest
—
PIC18F2455/2550/4455/4550
Preliminary
SYNC
CREN
BRG/EUSART Mode
SCKP
16-bit/Asynchronous
16-bit/Asynchronous
Bit 4
8-bit/Asynchronous
8-bit/Asynchronous
16-bit/Synchronous
8-bit/Synchronous
SENDB
ADDEN
BRG16
geous to use the high baud rate (BRGH = 1), or the
16-bit BRG to reduce the baud rate error, or achieve a
slow baud rate for a fast oscillator frequency.
Writing a new value to the SPBRGH:SPBRG registers
causes the BRG timer to be reset (or cleared). This
ensures the BRG does not wait for a timer overflow
before outputting the new baud rate.
20.1.1
The device clock is used to generate the desired baud
rate. When one of the power-managed modes is
entered, the new clock source may be operating at a
different frequency. This may require an adjustment to
the value in the SPBRG register pair.
20.1.2
The data on the RX pin is sampled three times by a
majority detect circuit to determine if a high or a low
level is present at the RX pin.
Bit 3
BRGH
FERR
Bit 2
OPERATION IN POWER-MANAGED
MODES
SAMPLING
—
OERR
TRMT
WUE
Bit 1
Baud Rate Formula
F
F
F
OSC
OSC
OSC
ABDEN
/[64 (n + 1)]
/[16 (n + 1)]
/[4 (n + 1)]
RX9D
TX9D
Bit 0
DS39632B-page 237
on page
Values
Reset
53
53
53
53
53