PIC18F2455-I/SP Microchip Technology, PIC18F2455-I/SP Datasheet - Page 419

• Manufacturer Part Number: PIC18F2455-I/SP
• Description: IC PIC MCU FLASH 12KX16 28DIP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F2455-I/SP

• Program Memory Type: FLASH
• Program Memory Size: 24KB (12K x 16)
• Package / Case: 28-DIP (0.300", 7.62mm)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 24
• Eeprom Size: 256 x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SPI/I2C/EAUSART
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 4
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DM163014, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10-ch x 10-bit
• Package: 28SPDIP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 48 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: I3-DB18F4550 - BOARD DAUGHTER ICEPIC3DM163025 - PIC DEM FULL SPEED USB DEMO BRDDVA18XP280 - DEVICE ADAPTER 18F2220 PDIP 28LD
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Table Reads/Table Writes ................................................. 60
TBLRD ............................................................................. 339
TBLWT ............................................................................. 340
Time-out in Various Situations (table) ................................ 47
Timer0 .............................................................................. 125
Timer1 .............................................................................. 129
Timer2 .............................................................................. 135
Timer3 .............................................................................. 137
Timing Diagrams
 2004 Microchip Technology Inc.
16-Bit Mode Timer Reads and Writes ...................... 126
Associated Registers ............................................... 127
Clock Source Edge Select (T0SE Bit) ...................... 126
Clock Source Select (T0CS Bit) ............................... 126
Operation ................................................................. 126
Overflow Interrupt .................................................... 127
Prescaler. See Prescaler, Timer0.
16-Bit Read/Write Mode ........................................... 131
Associated Registers ............................................... 133
Interrupt .................................................................... 132
Operation ................................................................. 130
Oscillator .......................................................... 129, 131
Overflow Interrupt .................................................... 129
Resetting, Using a Special Event
Special Event Trigger (ECCP) ................................. 150
TMR1H Register ...................................................... 129
TMR1L Register ....................................................... 129
Use as a Real-Time Clock ....................................... 132
Associated Registers ............................................... 136
Interrupt .................................................................... 136
Operation ................................................................. 135
Output ...................................................................... 136
PR2 Register .................................................... 146, 151
TMR2 to PR2 Match Interrupt .......................... 146, 151
16-Bit Read/Write Mode ........................................... 139
Associated Registers ............................................... 139
Operation ................................................................. 138
Oscillator .......................................................... 137, 139
Overflow Interrupt ............................................ 137, 139
Special Event Trigger (CCP) .................................... 139
TMR3H Register ...................................................... 137
TMR3L Register ....................................................... 137
A/D Conversion ........................................................ 393
Acknowledge Sequence .......................................... 226
Asynchronous Reception ......................................... 245
Asynchronous Transmission .................................... 243
Asynchronous Transmission
Automatic Baud Rate Calculation ............................ 241
Auto-Wake-up Bit (WUE) During
Auto-Wake-up Bit (WUE) During Sleep ................... 246
Baud Rate Generator with Clock
BRG Overflow Sequence ......................................... 241
BRG Reset Due to SDA Arbitration
Brown-out Reset (BOR) ........................................... 379
Bus Collision During a Repeated
Bus Collision During a Repeated
Layout Considerations ..................................... 132
Low-Power Option ........................................... 131
Using Timer1 as a Clock Source ..................... 131
Trigger Output (CCP) ....................................... 132
(Back to Back) ................................................. 243
Normal Operation ............................................ 246
Arbitration ........................................................ 220
During Start Condition ..................................... 229
Start Condition (Case 1) .................................. 230
Start Condition (Case 2) .................................. 230
PIC18F2455/2550/4455/4550
Preliminary
Bus Collision During a
Bus Collision During a
Bus Collision During a
Bus Collision During a
Bus Collision for Transmit and Acknowledge .......... 227
Capture/Compare/PWM (CCP) ............................... 381
CLKO and I/O .......................................................... 378
Clock Synchronization ............................................. 213
Clock/Instruction Cycle .............................................. 61
EUSART Synchronous Receive
EUSART Synchronous Transmission
Example SPI Master Mode (CKE = 0) ..................... 382
Example SPI Master Mode (CKE = 1) ..................... 383
Example SPI Slave Mode (CKE = 0) ....................... 384
Example SPI Slave Mode (CKE = 1) ....................... 385
External Clock (All Modes Except PLL) ................... 376
Fail-Safe Clock Monitor ........................................... 295
First Start Bit Timing ................................................ 221
Full-Bridge PWM Output .......................................... 155
Half-Bridge PWM Output ......................................... 154
High/Low-Voltage Detect Characteristics ................ 373
High-Voltage Detect (VDIRMAG = 1) ...................... 276
I
I
I
I
I
I
I
I
I
I
I
Low-Voltage Detect (VDIRMAG = 0) ....................... 275
Master SSP I
Master SSP I
PWM Auto-Shutdown (PRSEN = 0, Auto-Restart Dis-
PWM Auto-Shutdown (PRSEN = 1,
PWM Direction Change ........................................... 157
PWM Direction Change at Near
PWM Output ............................................................ 146
Repeat Start Condition ............................................ 222
Reset, Watchdog Timer (WDT),
Send Break Character Sequence ............................ 247
Slave Synchronization ............................................. 199
Slow Rise Time (MCLR Tied to V
SPI Mode (Master Mode) ........................................ 198
SPI Mode (Slave Mode with CKE = 0) ..................... 200
SPI Mode (Slave Mode with CKE = 1) ..................... 200
SPP Write Address and Data for USB
2
2
2
2
2
2
2
2
2
2
2
C Bus Data ............................................................ 386
C Bus Start/Stop Bits ............................................ 386
C Master Mode (7 or 10-Bit Transmission) ........... 224
C Master Mode (7-Bit Reception) ......................... 225
C Slave Mode (10-Bit Reception, SEN = 0) .......... 210
C Slave Mode (10-Bit Reception, SEN = 1) .......... 215
C Slave Mode (10-Bit Transmission) .................... 211
C Slave Mode (7-Bit Reception, SEN = 0) ............ 208
C Slave Mode (7-Bit Reception, SEN = 1) ............ 214
C Slave Mode (7-Bit Transmission) ...................... 209
C Slave Mode General Call Address
Start Condition (SCL = 0) ................................ 229
Start Condition (SDA only) .............................. 228
Stop Condition (Case 1) .................................. 231
Stop Condition (Case 2) .................................. 231
(Master/Slave) ................................................. 390
(Master/Slave) ................................................. 390
Sequence (7 or 10-Bit Address Mode) ............ 216
abled) .............................................................. 160
Auto-Restart Enabled) ..................................... 160
100% Duty Cycle ............................................. 157
Oscillator Start-up Timer (OST) and
Power-up Timer (PWRT) ................................. 379
V
(4 Wait States) ................................................. 189
DD
Rise > T
2
2
C Bus Data ....................................... 388
C Bus Start/Stop Bits ........................ 388
PWRT
) ............................................ 49
DD
DS39632B-page 417
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