PIC18F2455-I/SP Microchip Technology, PIC18F2455-I/SP Datasheet - Page 420

• Manufacturer Part Number: PIC18F2455-I/SP
• Description: IC PIC MCU FLASH 12KX16 28DIP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F2455-I/SP

• Program Memory Type: FLASH
• Program Memory Size: 24KB (12K x 16)
• Package / Case: 28-DIP (0.300", 7.62mm)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 24
• Eeprom Size: 256 x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SPI/I2C/EAUSART
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 4
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DM163014, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10-ch x 10-bit
• Package: 28SPDIP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 48 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: I3-DB18F4550 - BOARD DAUGHTER ICEPIC3DM163025 - PIC DEM FULL SPEED USB DEMO BRDDVA18XP280 - DEVICE ADAPTER 18F2220 PDIP 28LD
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F2455/2550/4455/4550
Timing Diagrams and Specifications ................................ 376
Top-of-Stack Access .......................................................... 58
DS39632B-page 418
SPP Write Address, Write and Read Data
Stop Condition Receive or Transmit Mode .............. 226
Streaming Parallel Port (PIC18F4455/4550) ........... 392
Synchronous Reception
Synchronous Transmission ...................................... 248
Synchronous Transmission (Through TXEN) .......... 249
Time-out Sequence on POR w/PLL
Time-out Sequence on Power-up
Time-out Sequence on Power-up
Time-out Sequence on Power-up
Timer0 and Timer1 External Clock .......................... 380
Transition for Entry to Idle Mode ................................ 40
Transition for Entry to SEC_RUN Mode .................... 37
Transition for Entry to Sleep Mode ............................ 39
Transition for Two-Speed Start-up
Transition for Wake from Idle to Run Mode ............... 40
Transition for Wake from Sleep (HSPLL) ................... 39
Transition from RC_RUN Mode to
Transition from SEC_RUN Mode to
Transition to RC_RUN Mode ..................................... 38
USB Signal ............................................................... 391
A/D Conversion Requirements ................................ 394
Capture/Compare/PWM
CLKO and I/O Requirements ................................... 378
EUSART Synchronous Receive
EUSART Synchronous Transmission
Example SPI Mode Requirements
Example SPI Mode Requirements
Example SPI Mode Requirements
Example SPI Mode Requirements
External Clock Requirements .................................. 376
I
I
Master SSP I
Master SSP I
PLL Clock ................................................................. 377
Reset, Watchdog Timer, Oscillator Start-up
Streaming Parallel Port Requirements
Timer0 and Timer1 External Clock
USB Full Speed Requirements ................................ 391
USB Low-Speed Requirements ............................... 391
2
2
C Bus Data Requirements (Slave Mode) .............. 387
C Bus Start/Stop Bits Requirements ..................... 386
(No Wait States) ............................................... 189
(Master Mode, SREN) ...................................... 250
Enabled (MCLR Tied to V
(MCLR Not Tied to V
(MCLR Not Tied to V
(MCLR Tied to V
(INTOSC to HSPLL) ......................................... 293
PRI_RUN Mode ................................................. 38
PRI_RUN Mode (HSPLL) .................................. 37
Requirements (CCP) ........................................ 381
Requirements ................................................... 390
Requirements ................................................... 390
(Master Mode, CKE = 0) .................................. 382
(Master Mode, CKE = 1) .................................. 383
(Slave Mode, CKE = 0) .................................... 384
(Slave Mode, CKE = 1) .................................... 385
Requirements ................................................... 388
Timer, Power-up Timer and
Brown-out Reset Requirements ....................... 379
(PIC18F4455/4550) ......................................... 392
Requirements ................................................... 380
2
2
C Bus Data Requirements ................ 389
C Bus Start/Stop Bits
DD
, V
DD
DD
DD
), Case 1 ....................... 48
), Case 2 ....................... 48
Rise T
DD
) ............................. 49
PWRT
) .............. 48
Preliminary
TQFP Packages and Special Features ........................... 299
TSTFSZ ........................................................................... 341
Two-Speed Start-up ................................................. 279, 293
Two-Word Instructions
TXSTA Register
U
Universal Serial Bus
USB RAM .......................................................................... 63
USB. See Universal Serial Bus.
Example Cases .......................................................... 62
BRGH Bit ................................................................. 237
Address Register (UADDR) ..................................... 170
and Streaming Parallel Port ..................................... 182
Associated Registers ............................................... 183
Buffer Descriptor Table ............................................ 171
Buffer Descriptors .................................................... 171
Class Specifications and Drivers ............................. 185
Descriptors ............................................................... 185
Endpoint Control ...................................................... 169
Enumeration ............................................................ 185
External Pull-up Resistors ....................................... 167
External Transceiver ................................................ 165
Eye Pattern Test Enable .......................................... 167
Firmware and Drivers .............................................. 183
Frame Number Registers ........................................ 170
Frames .................................................................... 184
Internal Pull-up Resistors ......................................... 167
Internal Transceiver ................................................. 165
Internal Voltage Regulator ....................................... 167
Interrupts ................................................................. 177
Layered Framework ................................................. 184
Oscillator Requirements .......................................... 183
Output Enable Monitor ............................................. 167
Overview .......................................................... 163, 184
Ping-Pong Buffer Configuration ............................... 167
Power ...................................................................... 184
Power Modes ........................................................... 182
RAM ......................................................................... 170
Speed ...................................................................... 185
Status and Control ................................................... 164
Transfer Types ......................................................... 184
UFRMH:UFRML Registers ...................................... 170
USB Memory ............................................................. 63
Address Validation ........................................... 174
Assignment in Different
BDnSTAT Register (CPU Mode) ..................... 172
BDnSTAT Register (SIE Mode) ....................... 174
Byte Count ....................................................... 174
Example ........................................................... 171
Memory Map .................................................... 175
Ownership ....................................................... 171
Ping-Pong Buffering ........................................ 175
Register Summary ........................................... 176
Status and Configuration ................................. 171
and USB Transactions ..................................... 177
Interrupt Logic .................................................. 177
Bus Power Only ............................................... 182
Dual Power with Self-Power
Self-Power Only ............................................... 182
Memory Map .................................................... 170
Buffering Modes ...................................... 176
Dominance .............................................. 182
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