AT32UC3B164-Z1UT Atmel, AT32UC3B164-Z1UT Datasheet - Page 197
![IC MCU AVR32 64KB FLASH 48-QFN](/photos/6/82/68297/48-qfn_sml.jpg)
AT32UC3B164-Z1UT
Manufacturer Part Number
AT32UC3B164-Z1UT
Description
IC MCU AVR32 64KB FLASH 48-QFN
Manufacturer
Atmel
Series
AVR®32 UC3r
Specifications of AT32UC3B164-Z1UT
Core Processor
AVR
Core Size
32-Bit
Speed
60MHz
Connectivity
I²C, IrDA, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
28
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-QFN Exposed Pad
Processor Series
AT32UC3x
Core
AVR32
Data Bus Width
32 bit
Data Ram Size
16 KB
Interface Type
2-Wire, SPI, USART
Maximum Clock Frequency
60 MHz
Number Of Programmable I/os
28
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR32, EWAVR32-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1101
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 6 Channel
Package
48QFN EP
Device Core
AVR32
Family Name
AT32
Maximum Speed
60 MHz
Operating Supply Voltage
1.8|3.3 V
For Use With
ATSTK600-TQFP48 - STK600 SOCKET/ADAPTER 48-TQFPATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMR770-1008 - ISP 4PORT ATMEL AVR32 MCU SPIATEVK1101 - KIT DEV/EVAL FOR AVR32 AT32UC3B
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT32UC3B164-Z1UT
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
- Current page: 197 of 692
- Download datasheet (11Mb)
Figure 18-3. SPI Transfer Format (NCPHA = 1, 8 bits per transfer)
Figure 18-4. SPI Transfer Format (NCPHA = 0, 8 bits per transfer)
32059K–03/2011
SPCK cycle (for reference)
SPCK cycle (for reference)
(from master)
(from slave)
(CPOL = 0)
(CPOL = 1)
(to slave)
(from master)
(from slave)
(CPOL = 0)
(CPOL = 1)
SPCK
SPCK
MOSI
MISO
(to slave)
NSS
SPCK
SPCK
MOSI
MISO
NSS
the NCPHA bit. These two parameters determine the edges of the clock signal on which data is
driven and sampled. Each of the two parameters has two possible states, resulting in four possi-
ble combinations that are incompatible with one another. Thus, a master/slave pair must use the
same parameter pair values to communicate. If multiple slaves are used and fixed in different
configurations, the master must reconfigure itself each time it needs to communicate with a dif-
ferent slave.
Table 18-2
Table 18-2.
Figure 18-3 on page 197
***
1
MSB
MSB
MSB
1
shows the four modes and corresponding parameter settings.
MSB
*** Not Defined, but normaly MSB of previous character received
SPI modes
2
6
6
2
SPI Mode
6
6
3
0
1
2
3
5
5
and
3
5
5
Figure 18-4 on page 197
4
4
4
4
4
4
5
3
3
5
3
3
6
2
2
6
2
2
show examples of data transfers.
7
1
1
CPOL
7
0
0
1
1
1
1
8
LSB
8
LSB
LSB
LSB
AT32UC3B
***
NCPHA
1
0
1
0
197
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