AT32UC3B164-Z1UT Atmel, AT32UC3B164-Z1UT Datasheet - Page 378
![IC MCU AVR32 64KB FLASH 48-QFN](/photos/6/82/68297/48-qfn_sml.jpg)
AT32UC3B164-Z1UT
Manufacturer Part Number
AT32UC3B164-Z1UT
Description
IC MCU AVR32 64KB FLASH 48-QFN
Manufacturer
Atmel
Series
AVR®32 UC3r
Specifications of AT32UC3B164-Z1UT
Core Processor
AVR
Core Size
32-Bit
Speed
60MHz
Connectivity
I²C, IrDA, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
28
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-QFN Exposed Pad
Processor Series
AT32UC3x
Core
AVR32
Data Bus Width
32 bit
Data Ram Size
16 KB
Interface Type
2-Wire, SPI, USART
Maximum Clock Frequency
60 MHz
Number Of Programmable I/os
28
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR32, EWAVR32-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1101
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 6 Channel
Package
48QFN EP
Device Core
AVR32
Family Name
AT32
Maximum Speed
60 MHz
Operating Supply Voltage
1.8|3.3 V
For Use With
ATSTK600-TQFP48 - STK600 SOCKET/ADAPTER 48-TQFPATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMR770-1008 - ISP 4PORT ATMEL AVR32 MCU SPIATEVK1101 - KIT DEV/EVAL FOR AVR32 AT32UC3B
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT32UC3B164-Z1UT
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
- Current page: 378 of 692
- Download datasheet (11Mb)
22.7.2
22.7.2.1
22.7.2.2
22.7.2.3
32059K–03/2011
USB Device Operation
Introduction
Power-On and reset
USB reset
In device mode, the USBB supports full- and low-speed data transfers.
In addition to the default control endpoint, six endpoints are provided, which can be configured
with the types isochronous, bulk or interrupt, as described in
The device mode starts in the Idle state, so the pad consumption is reduced to the minimum.
Figure 22-13 on page 378
Figure 22-13. Device Mode States
After a hardware reset, the USBB device mode is in the Reset state. In this state:
D+ or D- will be pulled up according to the selected speed as soon as the DETACH bit is written
to zero and VBus is present. See
When the USBB is enabled (USBE is written to one) in device mode (ID is one), its device mode
state goes to the Idle state with minimal power consumption. This does not require the USB
clock to be activated.
The USBB device mode can be disabled and reset at any time by disabling the USBB (by writing
a zero to USBE) or when host mode is engaged (ID is zero).
The USB bus reset is managed by hardware. It is initiated by a connected host.
When a USB reset is detected on the USB line, the following operations are performed by the
controller:
• The macro clock is stopped in order to minimize power consumption (FRZCLK is written to
• The internal registers of the device mode are reset.
• The endpoint banks are de-allocated.
• Neither D+ nor D- is pulled up (DETACH is written to one).
• All the endpoints are disabled, except the default control endpoint.
one).
describes the USBB device mode main states.
RESET
HW
| ID = 0
USBE = 0
“Device mode”
Reset
| ID = 0
& ID = 1
USBE = 0
state>
other
<any
USBE = 1
for further details.
Idle
Table 22-1 on page
AT32UC3B
362.
378
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