AT32UC3B164-Z1UT Atmel, AT32UC3B164-Z1UT Datasheet - Page 527
![IC MCU AVR32 64KB FLASH 48-QFN](/photos/6/82/68297/48-qfn_sml.jpg)
AT32UC3B164-Z1UT
Manufacturer Part Number
AT32UC3B164-Z1UT
Description
IC MCU AVR32 64KB FLASH 48-QFN
Manufacturer
Atmel
Series
AVR®32 UC3r
Specifications of AT32UC3B164-Z1UT
Core Processor
AVR
Core Size
32-Bit
Speed
60MHz
Connectivity
I²C, IrDA, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
28
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-QFN Exposed Pad
Processor Series
AT32UC3x
Core
AVR32
Data Bus Width
32 bit
Data Ram Size
16 KB
Interface Type
2-Wire, SPI, USART
Maximum Clock Frequency
60 MHz
Number Of Programmable I/os
28
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR32, EWAVR32-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1101
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 6 Channel
Package
48QFN EP
Device Core
AVR32
Family Name
AT32
Maximum Speed
60 MHz
Operating Supply Voltage
1.8|3.3 V
For Use With
ATSTK600-TQFP48 - STK600 SOCKET/ADAPTER 48-TQFPATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMR770-1008 - ISP 4PORT ATMEL AVR32 MCU SPIATEVK1101 - KIT DEV/EVAL FOR AVR32 AT32UC3B
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT32UC3B164-Z1UT
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
- Current page: 527 of 692
- Download datasheet (11Mb)
24.6.2
24.6.2.1
Figure 24-3. Functional View of the Channel Block Diagram
24.6.2.2
32059K–03/2011
PWM Channel
Block Diagram
Waveform Properties
Inputs from
Inputs from
Peripheral
generator
clock
Bus
divided clocks.
The clock generator is divided in three blocks:
Each linear divider can independently divide one of the clocks of the modulo n counter. The
selection of the clock to be divided is made according to the PREA (PREB) field of the Mode reg-
ister (MR). The resulting clock clkA (clkB) is the clock selected divided by DIVA (DIVB) field
value in the Mode register (MR).
After a reset of the PWM controller, DIVA (DIVB) and PREA (PREB) in the Mode register are
cleared. This implies that after reset clkA (clkB) are turned off.
At reset, all clocks provided by the modulo n counter are turned off except clock “clk”. This situa-
tion is also true when the PWM master clock is turned off through the Power Manager .
Each of the
The different properties of output waveforms are:
• A clock selector which selects one of the clocks provided by the clock generator described in
• An internal counter clocked by the output of the clock selector. This internal counter is
• A comparator used to generate events according to the internal counter value. It also
• the internal clock selection. The internal channel counter is clocked by one of the clocks
Selector
Channel
Section
incremented or decremented according to the channel configuration and comparators events.
The size of the internal counter is
computes the PWMx output waveform according to the configuration.
provided by the clock generator described in the previous section. This channel parameter is
defined in the CPRE field of the CMRx register. This field is reset at 0.
Clock
– a modulo n counter which provides 11 clocks: F
– two linear dividers (1, 1/2, 1/3, ... 1/255) that provide two separate clocks: clkA and
F
F
clkB
CLK_PWM
CLK_PWM
24.6.1.
7
channels is composed of three blocks:
/8, F
/512, F
CLK_PWM
Counter
Internal
CLK_PWM
/16, F
/1024
CLK_PWM
20
bits.
/32, F
Comparator
CLK_PWM
CLK_PWM
/64, F
CLK_PWM
, F
CLK_PWM
/128, F
PWMx output
waveform
/2, F
AT32UC3B
CLK_PWM
CLK_PWM
/256,
/4,
527
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