AT32UC3B164-Z1UT Atmel, AT32UC3B164-Z1UT Datasheet - Page 552
![IC MCU AVR32 64KB FLASH 48-QFN](/photos/6/82/68297/48-qfn_sml.jpg)
AT32UC3B164-Z1UT
Manufacturer Part Number
AT32UC3B164-Z1UT
Description
IC MCU AVR32 64KB FLASH 48-QFN
Manufacturer
Atmel
Series
AVR®32 UC3r
Specifications of AT32UC3B164-Z1UT
Core Processor
AVR
Core Size
32-Bit
Speed
60MHz
Connectivity
I²C, IrDA, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
28
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-QFN Exposed Pad
Processor Series
AT32UC3x
Core
AVR32
Data Bus Width
32 bit
Data Ram Size
16 KB
Interface Type
2-Wire, SPI, USART
Maximum Clock Frequency
60 MHz
Number Of Programmable I/os
28
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR32, EWAVR32-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1101
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 6 Channel
Package
48QFN EP
Device Core
AVR32
Family Name
AT32
Maximum Speed
60 MHz
Operating Supply Voltage
1.8|3.3 V
For Use With
ATSTK600-TQFP48 - STK600 SOCKET/ADAPTER 48-TQFPATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMR770-1008 - ISP 4PORT ATMEL AVR32 MCU SPIATEVK1101 - KIT DEV/EVAL FOR AVR32 AT32UC3B
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT32UC3B164-Z1UT
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
- Current page: 552 of 692
- Download datasheet (11Mb)
25.6.4
Figure 25-2. EOCn and DRDY Flag Behavior
32059K–03/2011
CHn(CHSR)
DRDY(SR)
EOCn(SR)
Conversion Results
With START=1
Write CR
as zero. The two highest bits of the Last Data Converted field in the Last Converted Data Regis-
ter (LCDR.LDATA) will be read as zero too.
Moreover, when a Peripheral DMA channel is connected to the ADC, a 10-bit resolution sets the
transfer request size to 16-bit. Writing a one to the LOWRES bit automatically switches to 8-bit
data transfers. In this case, the destination buffers are optimized.
When a conversion is completed, the resulting 10-bit digital value is stored in the CDR register of
the current channel and in the LCDR register. Channels are enabled by writing a one to the
Channel n Enable bit (CHn) in the CHER register.
The corresponding channel End of Conversion bit in the Status Register (SR.EOCn) and the
Data Ready bit in the SR register (SR.DRDY) are set. In the case of a connected Peripheral
DMA channel, DRDY rising triggers a data transfer request. In any case, either EOC or DRDY
can trigger an interrupt.
Reading one of the CDRn registers clears the corresponding EOC bit. Reading LCDR clears the
DRDY bit and the EOC bit corresponding to the last converted channel.
Conversion Time
Read CDRn
With START=1
Write CR
Conversion Time
AT32UC3B
Read LCDR
552
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