PIC32MX440F256H-80I/PT Microchip Technology, PIC32MX440F256H-80I/PT Datasheet - Page 298
![IC PIC MCU FLASH 256K 64-TQFP](/photos/6/81/68123/c04-066_pf_sml.jpg)
PIC32MX440F256H-80I/PT
Manufacturer Part Number
PIC32MX440F256H-80I/PT
Description
IC PIC MCU FLASH 256K 64-TQFP
Manufacturer
Microchip Technology
Series
PIC® 32MXr
Datasheets
1.MA320002.pdf
(208 pages)
2.DM320001.pdf
(44 pages)
3.PIC32MX320F032H-40IPT.pdf
(48 pages)
4.PIC32MX320F032H-40IPT.pdf
(66 pages)
5.PIC32MX320F032H-40IPT.pdf
(22 pages)
6.PIC32MX460F256L-80IPT.pdf
(632 pages)
7.PIC32MX320F064H-40IMR.pdf
(172 pages)
Specifications of PIC32MX440F256H-80I/PT
Program Memory Type
FLASH
Program Memory Size
256KB (256K x 8)
Package / Case
64-TFQFP
Core Processor
MIPS32® M4K™
Core Size
32-Bit
Speed
80MHz
Connectivity
I²C, IrDA, LIN, PMP, SPI, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
53
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC32MX4xx
Core
MIPS
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
I2C , SPI , UART
Maximum Clock Frequency
80 MHz
Number Of Programmable I/os
51
Number Of Timers
5 x 16 bit, 1 x 32 bit
Operating Supply Voltage
2.3 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, DM320003, DM320002, MA320002
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Controller Family/series
PIC32
Ram Memory Size
32KB
Cpu Speed
80MHz
No. Of Timers
5
Embedded Interface Type
EUSART, I2C, SPI, USB
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
876-1000 - PIC32 BREAKOUT BOARDAC244003 - TEST BD MPLAB REAL ICE LOOPBACKDM320003 - BOARD DEMO USB PIC32 OTGAC244006 - KIT MPLAB REAL ICE TRACEAC164327 - MODULE SKT FOR 64TQFP
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC32MX440F256H-80I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
PIC32MX440F256H-80I/PT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- MA320002 PDF datasheet
- DM320001 PDF datasheet #2
- PIC32MX320F032H-40IPT PDF datasheet #3
- PIC32MX320F032H-40IPT PDF datasheet #4
- PIC32MX320F032H-40IPT PDF datasheet #5
- PIC32MX460F256L-80IPT PDF datasheet #6
- PIC32MX320F064H-40IMR PDF datasheet #7
- Current page: 298 of 632
- Download datasheet (10Mb)
PIC32MX3XX/4XX
When the B-device has finished in its role as host, it
stops all bus activity and turns on its D+ pull-up resistor
by disabling host operations (HOSTEN = 0) and recon-
necting as a device (DPPULUP = 1).
Then the A-device detects a suspend condition (Idle for
3 ms), the A-device turns off its D+ pull-up. Alternatively
the A-device may also power-down the V
end the session.
When the A-device detects the connect condition (via
ATTACHIF), the A-device resumes host operation, and
drives Reset signaling.
11.33.2
For proper USB operation, the USB module must be
clocked with a 48 MHz clock. This clock source is used
to generate the timing for USB transfers; it is the clock
source for the SIE. The control registers are clocked at
the same speed as the CPU (refer to Figure 11-1).
The USB module clock is derived from the Primary
Oscillator (POSC) for USB operation. A USB PLL and
input prescalers are provided to allow 48 MHz clock
generation from a wide variety of input frequencies.
The USB PLL allows the CPU and the USB module to
operate at different frequencies while both use the
POSC as a clock source. To prevent buffer overruns
and timing issues, the CPU core must be clocked at a
minimum of 16 MHz.
The USB module can also use the on-board Fast RC
oscillator (FRC) as a clock source. When using this
clock source, the USB module will not meet the USB
timing requirements. The FRC clock source is intended
to allow the USB module to detect a USB wake-up and
report it to the interrupt controller when operating in
low-power modes. The USB module must be running
from the Primary oscillator before beginning USB
transmissions.
11.34 Interrupts
The USB module uses interrupts to signal USB events
such as a change in status, data received and buffer
empty events, to the CPU. Software must be able to
respond to these interrupts in a timely manner.
11.35 Interrupt Control
Each interrupt source in the USB module has an inter-
rupt flag bit and a corresponding enable bit. In addition,
the UERRIF bit (U1IR<1>) is a logical OR of all the
enabled error flags and is read-only. The UERRIF bit
can be used to poll the USB module for events while in
an Interrupt Service Routine (ISR).
DS61143C-page 296
CLOCK REQUIREMENTS
BUS
supply to
Preliminary
11.36 USB Module Interrupt Request
The USB module can generate interrupt requests from
a variety of events. To interface these interrupts to the
CPU, the USB interrupts are combined such that any
enabled USB interrupt will cause a generic USB inter-
rupt (if the USB interrupt is enabled) to the interrupt
controller, see Figure 11-11. The USB ISR must then
determine which USB event(s) caused the CPU inter-
rupt and service them appropriately. There are two lay-
ers of interrupt registers in the USB module. The top
level of bits consists of overall USB status interrupts in
the U1OTGIR and U1IR registers. The U1OTGIR and
U1IR bits are individually enabled through the corre-
sponding bits in the U1OTGIE and U1IE registers. In
addition, the USB Error Condition bit (UERRIF) passes
through any interrupt conditions in the U1EIR register
enabled via the U1EIE register bits.
11.37 Interrupt Timing
Interrupts for transfers are generated at the end of the
transfer. Figure 11-10 shows some typical event
sequences that can generate a USB interrupt and
when that interrupt is generated. There is no mecha-
nism by which software can manually set an interrupt
bit.
The values in the Interrupt Enable registers (U1IE,
U1EIE, U1OTGIE) only affect the propagation of an
interrupt condition to the CPU’s interrupt controller.
Even though an interrupt is not enabled, interrupt flag
bits can still be polled and serviced.
11.38 Interrupt Servicing
Once an interrupt bit has been set by the USB module
(in U1IR, U1EIR or U1OTGIR), it must be cleared by
software by writing a ‘1’ to the appropriate bit position
to clear the interrupt. The USB Interrupt, USBIF
(IFS1<25>), must be cleared before the end of the ISR.
Generation
© 2008 Microchip Technology Inc.
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