PIC32MX440F256H-80I/PT Microchip Technology, PIC32MX440F256H-80I/PT Datasheet - Page 459
![IC PIC MCU FLASH 256K 64-TQFP](/photos/6/81/68123/c04-066_pf_sml.jpg)
PIC32MX440F256H-80I/PT
Manufacturer Part Number
PIC32MX440F256H-80I/PT
Description
IC PIC MCU FLASH 256K 64-TQFP
Manufacturer
Microchip Technology
Series
PIC® 32MXr
Datasheets
1.MA320002.pdf
(208 pages)
2.DM320001.pdf
(44 pages)
3.PIC32MX320F032H-40IPT.pdf
(48 pages)
4.PIC32MX320F032H-40IPT.pdf
(66 pages)
5.PIC32MX320F032H-40IPT.pdf
(22 pages)
6.PIC32MX460F256L-80IPT.pdf
(632 pages)
7.PIC32MX320F064H-40IMR.pdf
(172 pages)
Specifications of PIC32MX440F256H-80I/PT
Program Memory Type
FLASH
Program Memory Size
256KB (256K x 8)
Package / Case
64-TFQFP
Core Processor
MIPS32® M4K™
Core Size
32-Bit
Speed
80MHz
Connectivity
I²C, IrDA, LIN, PMP, SPI, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
53
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC32MX4xx
Core
MIPS
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
I2C , SPI , UART
Maximum Clock Frequency
80 MHz
Number Of Programmable I/os
51
Number Of Timers
5 x 16 bit, 1 x 32 bit
Operating Supply Voltage
2.3 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, DM320003, DM320002, MA320002
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Controller Family/series
PIC32
Ram Memory Size
32KB
Cpu Speed
80MHz
No. Of Timers
5
Embedded Interface Type
EUSART, I2C, SPI, USB
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
876-1000 - PIC32 BREAKOUT BOARDAC244003 - TEST BD MPLAB REAL ICE LOOPBACKDM320003 - BOARD DEMO USB PIC32 OTGAC244006 - KIT MPLAB REAL ICE TRACEAC164327 - MODULE SKT FOR 64TQFP
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC32MX440F256H-80I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
PIC32MX440F256H-80I/PT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- MA320002 PDF datasheet
- DM320001 PDF datasheet #2
- PIC32MX320F032H-40IPT PDF datasheet #3
- PIC32MX320F032H-40IPT PDF datasheet #4
- PIC32MX320F032H-40IPT PDF datasheet #5
- PIC32MX460F256L-80IPT PDF datasheet #6
- PIC32MX320F064H-40IMR PDF datasheet #7
- Current page: 459 of 632
- Download datasheet (10Mb)
20.3.16
The Addressable Slave mode initialization properly
prepares the PSP port for communicating with an
external master device.
The following steps should be performed to properly
configure the PSP port:
1.
2.
EXAMPLE 20-6:
20.4
The PMP module has the ability to generate the follow-
ing types of interrupts reflecting the events that occur
during data transfers.
Master mode:
• Interrupt on every read and write operation.
Legacy Slave mode:
• Interrupt on every read and write byte
Buffered Slave mode:
• Interrupt on every read and write byte
• Interrupt on read or write byte of Buffer 3
• Interrupt on every read and write byte
• Interrupt on read or write byte of Buffer 3
The PMP module is enabled as a source of interrupt
using the PMP interrupt enable bit:
• PMPIE (IEC1<2>).
© 2008 Microchip Technology Inc.
Addressable Slave mode:
IEC1CLR = 0x0004
PMCON = 0x0000
PMMODE = 0x0100
IPC7SET = 0x001C;
IPC7SET = 0x0003;
IFS1CLR
IEC1SET
PMCONSET = 0x8000;
(PMDOUT<31:24>)
(PMDOUT<31:24>), PMA<1:0> = 11
If interrupts are used, disable the PMP interrupt
by clearing the interrupt enable bit PMPIE
(IEC1<2>) = 0.
Stop and reset the PMP module by clearing the
PMP Interrupts
ADDRESSABLE SLAVE PORT
INITIALIZATION
= 0x0004;
= 0x0004;
ADDRESSABLE PARALLEL SLAVE PORT INITIALIZATION
//Enable PMP module
//Clear PMP int flag
//Enable PMP int
//Disable PMP int
//Stop and Configure
//Config PMMODE
//Priority level=7
//subpriority=3
//Same as...
//IPC7SET=0x001F
Preliminary
3.
4.
5.
The interrupt priority level and subpriority level bits
must also be configured:
• The PMP interrupt status flag, PMPIF (IFS1<2>)
Below is a partial code example of an ISR.
is typically cleared by the user’s software in the
ISR.
Note:
- PMPIP<2:0> (IPC7<4:2>)
- PMPIS<1:0> (IPC7<1:0>)
control bit ON (PMCON<15>) = 0.
Configure the desired settings in the PMCON
and PMMODE control registers.
If interrupts are used:
a)
b)
c)
Enable the PMP slave port by setting control bit
ON = 1.
PIC32MX3XX/4XX
Clear interrupt flag bit PMPIF
(IFS1<2>) = 0.
Configure the PMP interrupt priority bits
PMPIP<2:0> (IPC7<4:2>) and interrupt sub
priority bits PMPIS (IPC7<1:0>.
Enable PSP interrupt by setting interrupt
enable bit PMPIE = 1.
It is the user’s responsibility to clear the
corresponding interrupt flag bit before
returning from an ISR.
DS61143C-page 457
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