PIC32MX440F256H-80I/PT Microchip Technology, PIC32MX440F256H-80I/PT Datasheet - Page 553
![IC PIC MCU FLASH 256K 64-TQFP](/photos/6/81/68123/c04-066_pf_sml.jpg)
PIC32MX440F256H-80I/PT
Manufacturer Part Number
PIC32MX440F256H-80I/PT
Description
IC PIC MCU FLASH 256K 64-TQFP
Manufacturer
Microchip Technology
Series
PIC® 32MXr
Datasheets
1.MA320002.pdf
(208 pages)
2.DM320001.pdf
(44 pages)
3.PIC32MX320F032H-40IPT.pdf
(48 pages)
4.PIC32MX320F032H-40IPT.pdf
(66 pages)
5.PIC32MX320F032H-40IPT.pdf
(22 pages)
6.PIC32MX460F256L-80IPT.pdf
(632 pages)
7.PIC32MX320F064H-40IMR.pdf
(172 pages)
Specifications of PIC32MX440F256H-80I/PT
Program Memory Type
FLASH
Program Memory Size
256KB (256K x 8)
Package / Case
64-TFQFP
Core Processor
MIPS32® M4K™
Core Size
32-Bit
Speed
80MHz
Connectivity
I²C, IrDA, LIN, PMP, SPI, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
53
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC32MX4xx
Core
MIPS
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
I2C , SPI , UART
Maximum Clock Frequency
80 MHz
Number Of Programmable I/os
51
Number Of Timers
5 x 16 bit, 1 x 32 bit
Operating Supply Voltage
2.3 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, DM320003, DM320002, MA320002
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Controller Family/series
PIC32
Ram Memory Size
32KB
Cpu Speed
80MHz
No. Of Timers
5
Embedded Interface Type
EUSART, I2C, SPI, USB
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
876-1000 - PIC32 BREAKOUT BOARDAC244003 - TEST BD MPLAB REAL ICE LOOPBACKDM320003 - BOARD DEMO USB PIC32 OTGAC244006 - KIT MPLAB REAL ICE TRACEAC164327 - MODULE SKT FOR 64TQFP
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC32MX440F256H-80I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
PIC32MX440F256H-80I/PT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- MA320002 PDF datasheet
- DM320001 PDF datasheet #2
- PIC32MX320F032H-40IPT PDF datasheet #3
- PIC32MX320F032H-40IPT PDF datasheet #4
- PIC32MX320F032H-40IPT PDF datasheet #5
- PIC32MX460F256L-80IPT PDF datasheet #6
- PIC32MX320F064H-40IMR PDF datasheet #7
- Current page: 553 of 632
- Download datasheet (10Mb)
26.2
This describes the operation of the Watchdog Timer
operation and the Power-up Timer
26.2.1
If enabled, the WDT will increment until it overflows or
“times out”. A WDT time-out will force a device Reset,
except during Sleep or Idle modes. To prevent a WDT
time-out Reset, the user must periodically clear the
Watchdog
(WDTCON<0>) bit.
The WDT uses the LPRC oscillator for reliability.
26.2.2
The WDT is enabled or disabled by the device configu-
ration or controlled via software by writing to the
WDTCON register.
26.2.3
If the FWDTEN Configuration bit is set, then the WDT
is always enabled. The WDT ON control bit
(WDTCON<15>) will reflect this by reading a ‘1’. In this
mode, the ON bit cannot be cleared in software. This bit
will not be cleared by any form of Reset. To disable the
WDT in this mode, the configuration must be rewritten
to the device.
26.2.4
If the FWDTEN Configuration bit is a ‘0’, then the WDT
can be enabled or disabled (the default condition) by
software. In this mode, the ON (WDTCON<15>) bit
reflects the status of the WDT under software control.
A ‘1’ indicates the WDT is enabled and a ‘0’ indicates it
is disabled.
The WDT is enabled in software by setting the WDT
ON control bit. The WDT ON control bit is cleared on
any device Reset, The bit is not cleared upon a wake
from Sleep or exit from Idle mode. The software WDT
option allows the user to enable the WDT for critical
code segments and disable the WDT during noncritical
segments for maximum power savings. This bit can
also be used to disable the WDT while the part is
awake to eliminate the need for WDT servicing, and
then re-enable it before the device is put into Idle or
Sleep to wake the part at a later time.
© 2008 Microchip Technology Inc.
Note:
Note:
Watchdog Timer and Power-Up
Timer Operation
WATCHDOG TIMER OPERATION
ENABLING AND DISABLING THE
WDT
DEVICE CONFIGURATION
CONTROLLED WDT
SOFTWARE CONTROLLED WDT
The LPRC is enabled whenever the WDT
is enabled.
The default state for the WDT on an
unprogrammed device is WDT enabled.
Timer
by
setting
the
WDTCLR
Preliminary
26.2.5
The WDT, if enabled, will continue operation in Sleep or
Idle modes. The WDT may be used to wake the device
from Sleep or Idle. When the WDT times out in a Power
Save mode, a Non-Maskable Interrupt (NMI) is gener-
ated and the WDTO (RCON<4>) bit is set. The NMI
vectors execution to the CPU start-up address but does
not reset registers or peripherals. If the device was in
Sleep, the SLEEP (RCON<3>) status bit will also be
set. If the device was in Idle, the IDLE (RCON<2>) sta-
tus bit will also be set. These bits allow the start-up
code to determine the cause of the wake-up.
26.2.6
There will be a time delay between the WDT event in
Sleep and the beginning of code execution. The dura-
tion of this delay consists of the Start-up time for the
oscillator in use and the Power-up Timer delay, if it is
enabled.
Unlike a wake-up from Sleep mode, there are no time
delays associated with wake-up from Idle mode. The
system clock is running during Idle mode; therefore, no
start-up delays are required at wake-up.
26.2.7
The WDT is reset by any of the following:
• On ANY device Reset
• By a WDTCONSET = 0x01 or equivalent
• Execution of a DEBUG command
• Exiting from Idle or Sleep due to an interrupt
26.2.8
The WDT clock source is the internal LPRC oscillator,
which has a nominal frequency of 32 kHz. This creates
a nominal time-out period for the WDT (T
millisecond when no postscaler is used.
instruction during normal execution.
Note:
Note:
PIC32MX3XX/4XX
WDT OPERATION IN POWER SAVE
MODES
RESETTING THE WDT TIMER
WDT TIMER PERIOD SELECTION
The WDT timer is not reset when the
device enters a Power Save mode. The
WDT should be serviced prior to entering
a Power Save mode.
The WDT time-out period is directly
related to the frequency of the LPRC
oscillator.
oscillator will vary as a function of device
operating
Please
PIC32MX3XX/4XX device data sheet for
LPRC clock frequency specifications.
TIME DELAYS ON WAKE
refer
The frequency of the LPRC
voltage and temperature.
to
DS61143C-page 551
the
WDT
specific
) of 1
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