PIC32MX440F256H-80I/PT Microchip Technology, PIC32MX440F256H-80I/PT Datasheet - Page 350
![IC PIC MCU FLASH 256K 64-TQFP](/photos/6/81/68123/c04-066_pf_sml.jpg)
PIC32MX440F256H-80I/PT
Manufacturer Part Number
PIC32MX440F256H-80I/PT
Description
IC PIC MCU FLASH 256K 64-TQFP
Manufacturer
Microchip Technology
Series
PIC® 32MXr
Datasheets
1.MA320002.pdf
(208 pages)
2.DM320001.pdf
(44 pages)
3.PIC32MX320F032H-40IPT.pdf
(48 pages)
4.PIC32MX320F032H-40IPT.pdf
(66 pages)
5.PIC32MX320F032H-40IPT.pdf
(22 pages)
6.PIC32MX460F256L-80IPT.pdf
(632 pages)
7.PIC32MX320F064H-40IMR.pdf
(172 pages)
Specifications of PIC32MX440F256H-80I/PT
Program Memory Type
FLASH
Program Memory Size
256KB (256K x 8)
Package / Case
64-TFQFP
Core Processor
MIPS32® M4K™
Core Size
32-Bit
Speed
80MHz
Connectivity
I²C, IrDA, LIN, PMP, SPI, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
53
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC32MX4xx
Core
MIPS
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
I2C , SPI , UART
Maximum Clock Frequency
80 MHz
Number Of Programmable I/os
51
Number Of Timers
5 x 16 bit, 1 x 32 bit
Operating Supply Voltage
2.3 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, DM320003, DM320002, MA320002
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Controller Family/series
PIC32
Ram Memory Size
32KB
Cpu Speed
80MHz
No. Of Timers
5
Embedded Interface Type
EUSART, I2C, SPI, USB
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
876-1000 - PIC32 BREAKOUT BOARDAC244003 - TEST BD MPLAB REAL ICE LOOPBACKDM320003 - BOARD DEMO USB PIC32 OTGAC244006 - KIT MPLAB REAL ICE TRACEAC164327 - MODULE SKT FOR 64TQFP
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC32MX440F256H-80I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
PIC32MX440F256H-80I/PT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- MA320002 PDF datasheet
- DM320001 PDF datasheet #2
- PIC32MX320F032H-40IPT PDF datasheet #3
- PIC32MX320F032H-40IPT PDF datasheet #4
- PIC32MX320F032H-40IPT PDF datasheet #5
- PIC32MX460F256L-80IPT PDF datasheet #6
- PIC32MX320F064H-40IMR PDF datasheet #7
- Current page: 350 of 632
- Download datasheet (10Mb)
PIC32MX3XX/4XX
14.4
A timer can generate an interrupt on a period match
event or a gate event, caused by the falling edge of the
external gate signal.
A timer sets its corresponding interrupt flag bit, TxIF,
whenever the timer event is generated. Refer to a
specific timer mode for details regarding these event
conditions. When a timer event is generated, the inter-
rupt flag bit is set within 1 PBCLK + 2 SYSCLK cycles.
If the timer interrupt enable bit is set, TxIE = 1, an
interrupt is generated.
EXAMPLE 14-7:
EXAMPLE 14-8:
DS61143C-page 348
T4CON = 0x0;
T5CON = 0x0;
T4CONSET = 0x0038;
TMR4= 0x0;
PR4 = 0xFFFFFFFF;
IPC5SET = 0x00000004; // Set priority level=1 and
IPC5SET = 0x00000001; // Set subpriority level=1
IFS0CLR = 0x10000000; // Clear the Timer5 interrupt status flag
IEC0SET = 0x10000000; // Enable Timer5 interrupts
T4CONSET = 0x8000;
T2CON = 0x0;
TMR2 = 0x0;
PR2 = 0xFFFF;
IPC2SET = 0x0000000C; // Set priority level=3
IPC2SET = 0x00000001; // Set subpriority level=1
IFS0CLR = 0x00000100; // Clear Timer interrupt status flag
IEC0SET = 0x00000100; // Enable Timer interrupts
T2CONSET = 0x8000;
Timer Interrupts
16-BIT TIMER INTERRUPT AND PRIORITIES
32-BIT TIMER INTERRUPT AND PRIORITIES
// Stop 16-bit Timer4 and clear control register
// Stop 16-bit Timer5 and clear control register
// Enable 32-bit mode, prescaler at 1:8,
// internal clock source
// Clear contents of the TMR4 and TMR5
// registers in one 32-bit load operation
// Load PR4 and PR5 registers with 32-bit value
// 0xFFFFFFFF in one 32-bit load operation
// Could have also done this in single
// operation by assigning IPC5SET = 0x00000005
// Start Timer
// prescaler at 1:1,internal clock source
// Clear timer register
// Load period register
// Could have also done this in single
// operation by assigning IPC2SET = 0x0000000D
// Start Timer
// Stop Timer and clear control register,
Preliminary
The timer module is enabled as a source of interrupts
via the respective Timer Interrupt Enable bit, TxIE
(IECx<n>). The Timer Interrupt Flag, TxIF (IFSx<n>),
must be cleared in software.
The interrupt priority level bits and interrupt subpriority
level bits must be also be configured:
• TxIP<2:0> (IPCx<4:2>)
• TxIS<1:0> (IPCx<1:0)
Setting the timer’s interrupt priority level = 0 effectively
disables the timer’s ability to generate an interrupt.
In addition to enabling the timer interrupt, an Interrupt
Service Routine, ISR, is required. Example 14-7
through Example 14-9 show a partial code example of
an ISR.
© 2008 Microchip Technology Inc.
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