PIC32MX440F256H-80I/PT Microchip Technology, PIC32MX440F256H-80I/PT Datasheet - Page 321

• Manufacturer Part Number: PIC32MX440F256H-80I/PT
• Description: IC PIC MCU FLASH 256K 64-TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX440F256H-80I/PT

• Program Memory Type: FLASH
• Program Memory Size: 256KB (256K x 8)
• Package / Case: 64-TFQFP
• Core Processor: MIPS32® M4K™
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: I²C, IrDA, LIN, PMP, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 53
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC32MX4xx
• Core: MIPS
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: I2C , SPI , UART
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 51
• Number Of Timers: 5 x 16 bit, 1 x 32 bit
• Operating Supply Voltage: 2.3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, DM320003, DM320002, MA320002
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Controller Family/series: PIC32
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• No. Of Timers: 5
• Embedded Interface Type: EUSART, I2C, SPI, USB
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1000 - PIC32 BREAKOUT BOARDAC244003 - TEST BD MPLAB REAL ICE LOOPBACKDM320003 - BOARD DEMO USB PIC32 OTGAC244006 - KIT MPLAB REAL ICE TRACEAC164327 - MODULE SKT FOR 64TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

12.2.6
In addition to the PORT, LAT and TRIS registers for
data control, each port pin configured as a digital output
can also select between an active drive output and
open-drain output. This is controlled by the Open-Drain
Control register, ODCx, associated with each port.
From POR, when an IO pin is configured as a digital
output, its output is active drive by default. Setting a bit
in the ODCx register = 1 configures the corresponding
pin as an open-drain output.
The open-drain feature allows the generation of
outputs higher than V
digital-only pins by using external pull-up resistors. The
maximum open-drain voltage allowed is the same as
the maximum V
12.2.7
In many cases, I/O pins are multiplexed with more than
one peripheral. A parallel I/O port pin that is multiplexed
with a peripheral is, in general, subordinate to the
peripheral.
When a peripheral is enabled and actively driving the
multiplexed pin, the use of the pin as a general purpose
output pin is disabled. The I/O pin may be read, but the
output driver for the parallel port bit will be disabled. If,
however, a peripheral is enabled, but the peripheral is
not actively driving a pin, that pin may be driven by a
port.
The peripheral’s output buffer data and control signals
are provided to a pair of multiplexers. The multiplexers
select whether the peripheral or the associated port
has ownership of the output data and control signals of
the I/O pin. The logic also prevents “loop through”, in
which a port’s digital output can drive the input of a
peripheral that shares the same pin. Figure 12-2 shows
how ports are shared with other peripherals and the
associated I/O pin to which they are connected.
In general, the dominant output control of a multiplexed
I/O pin can be determined by the order of the peripheral
output names assigned to a pin (read from left to right).
Multiplexed peripheral inputs have no priority.
For example, a pin labeled “U1TX/RF3”, indicates the
UART1 Transmit output, if enabled, has a higher prece-
dence over PORTF and therefore overrides the output
control of this pin.
© 2008 Microchip Technology Inc.
OPEN-DRAIN CONFIGURATION
PERIPHERAL MULTIPLEXING
IH
specification, typically 5.5v.
DD
, e.g., 5V, on any desired
Preliminary
12.2.8
Some peripheral inputs assigned to an I/O pin may not
take control of the I/O pin output driver. If the I/O pin
associated with the peripheral is configured as an out-
put, using the appropriate TRIS control bit, the user can
manually affect the state of the peripheral’s input pin
through its corresponding LAT register. This behavior
can be useful in some situations, especially for testing
purposes, when no external signal is connected to the
input pin.
In general, the following peripherals allow their input
pins to be controlled manually through the LAT
registers:
• External Interrupt pins
• Timer Clock Input pins
• Input Capture pins
• PWM Fault pins
Most serial communication peripherals, when enabled,
take full control of the I/O pin so that the input pins
associated with the peripheral cannot be affected
through the corresponding PORT registers. These
peripherals include the following modules:
• SPI
• I
• UART
Note:
2
C™
PIC32MX3XX/4XX
JTAG program/debug port is multiplexed
with PORTA pins RA0, RA1, RA4 and RA5
on 100-pin devices; PORTB pins RB10,
RB11, RB12 and RB13 on 64-pin devices. At
power-on-reset, these pins are controlled by
the JTAG port. To use these pins as general
purpose I/O pins, the user’s application code
must clear JTAGEN (DDPCON<3>) bit = 0.
To maintain these pins for JTAG pro-
gram/debug, the user’s application code
must maintain JTAGEN bit = 1.
SOFTWARE INPUT PIN CONTROL
DS61143C - page 319