PIC18F8720-I/PT Microchip Technology, PIC18F8720-I/PT Datasheet - Page 109

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PIC18F8720-I/PT

Manufacturer Part Number
PIC18F8720-I/PT
Description
IC MCU FLASH 64KX16 EE 80TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Fr

Specifications of PIC18F8720-I/PT

Program Memory Type
FLASH
Program Memory Size
128KB (64K x 16)
Package / Case
80-TFQFP
Core Processor
PIC
Core Size
8-Bit
Speed
25MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
68
Eeprom Size
1K x 8
Ram Size
3.75K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3.75 KB
Interface Type
I2C/SPI/USART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
68
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DM183032, DM183022, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
16-ch x 10-bit
Package
80TQFP
Device Core
PIC
Family Name
PIC18
Maximum Speed
25 MHz
Operating Supply Voltage
5 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT80PT3 - SOCKET TRAN ICE 80MQFP/TQFPAC164320 - MODULE SKT MPLAB PM3 80TQFPAC174011 - MODULE SKT PROMATEII 80TQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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FIGURE 10-6:
FIGURE 10-7:
 2004 Microchip Technology Inc.
Note 1:
2:
3:
Note 1:
I/O pin has diode protection to V
To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (INTCON2<7>).
The CCP2 input/output is multiplexed with RB3 if the CCP2MX bit is enabled (= 0) in the Configuration register and the device
is operating in Microprocessor, Microprocessor with Boot Block or Extended Microcontroller mode.
PIC18F6520/8520/6620/8620/6720/8720
2:
RBPU
Data Bus
RD TRISB
RD LATB
RD PORTB
BLOCK DIAGRAM OF RB2:RB0 PINS
BLOCK DIAGRAM OF RB3 PIN
CCP2MX
CCP Output
Enable
CCP Output
WR LATB or
WR PORTB
WR TRISB
RD PORTB
CCP2 or INT3
I/O pins have diode protection to V
To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION_REG<7>).
(2)
(3)
RBPU
Data Bus
RD TRIS
RD Port
INTx
WR Port
WR TRIS
(3)
(2)
Schmitt Trigger
Buffer
TRIS Latch
Data Latch
D
D
CK
CK
DD
and V
Q
Q
CCP2MX = 0
SS
DD
.
Data Latch
TRIS Latch
D
D
and V
CK
CK
Q
1
0
Schmitt Trigger
Buffer
SS
Q
Q
EN
.
D
Q
EN
D
TTL
Input
Buffer
V
V
N
P
DD
SS
V
P
RD Port
DD
TTL
Input
Buffer
Weak
Pull-up
I/O pin
V
P
DD
(1)
Weak
Pull-up
I/O pin
(1)
DS39609B-page 107

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