PIC18F8720-I/PT Microchip Technology, PIC18F8720-I/PT Datasheet - Page 374

• Manufacturer Part Number: PIC18F8720-I/PT
• Description: IC MCU FLASH 64KX16 EE 80TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F8720-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 128KB (64K x 16)
• Package / Case: 80-TFQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 68
• Eeprom Size: 1K x 8
• Ram Size: 3.75K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3.75 KB
• Interface Type: I2C/SPI/USART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 68
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DM183032, DM183022, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• Package: 80TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 25 MHz
• Operating Supply Voltage: 5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT80PT3 - SOCKET TRAN ICE 80MQFP/TQFPAC164320 - MODULE SKT MPLAB PM3 80TQFPAC174011 - MODULE SKT PROMATEII 80TQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F6520/8520/6620/8620/6720/8720
Software Simulator (MPLAB SIM) .................................... 302
Software Simulator (MPLAB SIM30) ................................ 302
Special Event Trigger. See Compare
Special Features of the CPU ............................................ 239
Special Function Registers ................................................ 47
SPI
SPI Master/Slave Connection .......................................... 161
SPI Module
SS .................................................................................... 157
SSP
SSPOV Status Flag .......................................................... 187
SSPSTAT Register
Status Bits
SUBFWB .......................................................................... 294
SUBLW ............................................................................ 295
SUBWF ............................................................................ 295
SUBWFB .......................................................................... 296
SWAPF ............................................................................ 296
T
Table Pointer Operations (table) ........................................ 64
TBLRD ............................................................................. 297
TBLWT ............................................................................. 298
Time-out in Various Situations ........................................... 31
Timer0 .............................................................................. 131
Timer0 and Timer1 External Clock
Timer1 .............................................................................. 135
DS39609B-page 372
Configuration Registers ................................... 240–249
Map ............................................................................ 50
Serial Clock .............................................................. 157
Serial Data In ........................................................... 157
Serial Data Out ........................................................ 157
Slave Select ............................................................. 157
SPI Mode ................................................................. 157
Associated Registers ............................................... 165
Bus Mode Compatibility ........................................... 165
Effects of a Reset ..................................................... 165
Master/Slave Connection ......................................... 161
Slave Mode .............................................................. 163
Sleep Operation ....................................................... 165
TMR2 Output for Clock Shift ............................ 141, 142
TMR4 Output for Clock Shift .................................... 148
R/W Bit ............................................................. 170, 171
Significance and Initialization Condition
16-bit Mode Timer Reads and Writes ...................... 133
Associated Registers ............................................... 133
Clock Source Edge Select (T0SE Bit) ...................... 133
Clock Source Select (T0CS Bit) ............................... 133
Operation ................................................................. 133
Overflow Interrupt .................................................... 133
Prescaler. See Prescaler, Timer0.
Requirements ........................................................... 328
16-bit Read/Write Mode ........................................... 138
Associated Registers ............................................... 139
Operation ................................................................. 136
Oscillator .......................................................... 135, 137
Overflow Interrupt ............................................ 135, 138
Special Event Trigger (CCP) ............................ 138, 152
TMR1H Register ...................................................... 135
TMR1L Register ....................................................... 135
Use as a Real-Time Clock ....................................... 138
for RCON Register ............................................. 31
Timer2 .............................................................................. 141
Timer3 .............................................................................. 143
Timer4 .............................................................................. 147
Timing Diagrams
Associated Registers ............................................... 142
Operation ................................................................. 141
Postscaler. See Postscaler, Timer2.
PR2 Register ................................................... 141, 154
Prescaler. See Prescaler, Timer2.
SSP Clock Shift ............................................... 141, 142
TMR2 Register ......................................................... 141
TMR2 to PR2 Match Interrupt .................. 141, 142, 154
Associated Registers ............................................... 145
Operation ................................................................. 144
Oscillator .......................................................... 143, 145
Overflow Interrupt ............................................ 143, 145
Special Event Trigger (CCP) ................................... 145
TMR3H Register ...................................................... 143
TMR3L Register ....................................................... 143
Associated Registers ............................................... 148
Operation ................................................................. 147
Postscaler. See Postscaler, Timer4.
PR4 Register ........................................................... 147
Prescaler. See Prescaler, Timer4.
SSP Clock Shift ....................................................... 148
TMR4 Register ......................................................... 147
TMR4 to PR4 Match Interrupt .......................... 147, 148
A/D Conversion ........................................................ 340
Acknowledge Sequence .......................................... 190
Baud Rate Generator with Clock Arbitration ............ 184
BRG Reset Due to SDA Arbitration
Brown-out Reset (BOR) ........................................... 327
Bus Collision During a Repeated
Bus Collision During a Repeated
Bus Collision During a Stop Condition
Bus Collision During a Stop Condition
Bus Collision During Start Condition
Bus Collision During Start Condition
Bus Collision for Transmit and Acknowledge .......... 191
Capture/Compare/PWM (All CCP Modules) ............ 328
CLKO and I/O .......................................................... 323
Clock Synchronization ............................................. 177
Clock/Instruction Cycle .............................................. 44
Example SPI Master Mode (CKE = 0) ..................... 330
Example SPI Master Mode (CKE = 1) ..................... 331
Example SPI Slave Mode (CKE = 0) ....................... 332
Example SPI Slave Mode (CKE = 1) ....................... 333
External Clock (All Modes except PLL) ................... 322
External Memory Bus for Sleep
External Memory Bus for TBLRD
External Memory Bus for TBLRD
I
I
I
I
2
2
2
2
C Bus Data ............................................................ 335
C Bus Start/Stop Bits ............................................ 334
C Master Mode (7 or 10-bit Transmission) ............ 188
C Master Mode (7-bit Reception) .......................... 189
During Start Condition ..................................... 193
Start Condition (Case 1) .................................. 194
Start Condition (Case 2) .................................. 194
(Case 1) ........................................................... 195
(Case 2) ........................................................... 195
(SCL = 0) ......................................................... 193
(SDA only) ....................................................... 192
(Microprocessor Mode) ...................................... 77
(Extended Microcontroller Mode) ...................... 76
(Microprocessor Mode) ...................................... 76
 2004 Microchip Technology Inc.