PIC18F8720-I/PT Microchip Technology, PIC18F8720-I/PT Datasheet - Page 261

• Manufacturer Part Number: PIC18F8720-I/PT
• Description: IC MCU FLASH 64KX16 EE 80TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F8720-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 128KB (64K x 16)
• Package / Case: 80-TFQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 68
• Eeprom Size: 1K x 8
• Ram Size: 3.75K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3.75 KB
• Interface Type: I2C/SPI/USART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 68
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DM183032, DM183022, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• Package: 80TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 25 MHz
• Operating Supply Voltage: 5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT80PT3 - SOCKET TRAN ICE 80MQFP/TQFPAC164320 - MODULE SKT MPLAB PM3 80TQFPAC174011 - MODULE SKT PROMATEII 80TQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

24.0
The PIC18 instruction set adds many enhancements to
the previous PICmicro instruction sets, while maintain-
ing an easy migration from these PICmicro instruction
sets.
Most instructions are a single program memory word
(16 bits), but there are three instructions that require
two program memory locations.
Each single-word instruction is a 16-bit word divided
into an opcode, which specifies the instruction type and
one or more operands, which further specify the
operation of the instruction.
The instruction set is highly orthogonal and is grouped
into four basic categories:
• Byte-oriented operations
• Bit-oriented operations
• Literal operations
• Control operations
The PIC18 instruction set summary in Table 24-1 lists
byte-oriented, bit-oriented, literal and control
operations. Table 24-1 shows the opcode field
descriptions.
Most byte-oriented instructions have three operands:
1.
2.
3.
The file register designator ‘f’ specifies which file
register is to be used by the instruction.
The destination designator ‘d’ specifies where the
result of the operation is to be placed. If ‘d’ is zero, the
result is placed in the WREG register. If ‘d’ is one, the
result is placed in the file register specified in the
instruction.
All bit-oriented instructions have three operands:
1.
2.
3.
The bit field designator ‘b’ selects the number of the bit
affected by the operation, while the file register desig-
nator ‘f’ represents the number of the file in which the
bit is located.
 2004 Microchip Technology Inc.
The file register (specified by ‘f’)
The destination of the result
(specified by ‘d’)
The accessed memory
(specified by ‘a’)
The file register (specified by ‘f’)
The bit in the file register
(specified by ‘b’)
The accessed memory
(specified by ‘a’)
INSTRUCTION SET SUMMARY
PIC18F6520/8520/6620/8620/6720/8720
The literal instructions may use some of the following
operands:
• A literal value to be loaded into a file register
• The desired FSR register to load the literal value
• No operand required
The control instructions may use some of the following
operands:
• A program memory address (specified by ‘n’)
• The mode of the CALL or RETURN instructions
• The mode of the table read and table write
• No operand required
All instructions are a single word, except for three
double-word instructions. These three instructions
were made double-word instructions so that all the
required information is available in these 32 bits. In the
second word, the 4 MSbs are ‘1’s. If this second word
is executed as an instruction (by itself), it will execute
as a NOP.
All single-word instructions are executed in a single
instruction cycle, unless a conditional test is true or the
program counter is changed as a result of the instruc-
tion. In these cases, the execution takes two instruction
cycles, with the additional instruction cycle(s) executed
as a NOP.
The double-word instructions execute in two instruction
cycles.
One instruction cycle consists of four oscillator periods.
Thus, for an oscillator frequency of 4 MHz, the normal
instruction execution time is 1 s. If a conditional test is
true, or the program counter is changed as a result of
an instruction, the instruction execution time is 2 s.
Two-word branch instructions (if true) would take 3 s.
Figure 24-1 shows the general formats that the
instructions can have.
All examples use the format ‘nnh’ to represent a hexa-
decimal number, where ‘h’ signifies a hexadecimal
digit.
The Instruction Set Summary, shown in Table 24-1,
lists the instructions recognized by the Microchip
Assembler (MPASM
Section 24.1 “Instruction Set” provides a description
of each instruction.
(specified by ‘k’)
into (specified by ‘f’)
(specified by ‘—’)
(specified by ‘s’)
instructions (specified by ‘m’)
(specified by ‘—’)
TM
).
DS39609B-page 259