PIC18F8720-I/PT Microchip Technology, PIC18F8720-I/PT Datasheet - Page 208

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PIC18F8720-I/PT

Manufacturer Part Number
PIC18F8720-I/PT
Description
IC MCU FLASH 64KX16 EE 80TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Fr

Specifications of PIC18F8720-I/PT

Program Memory Type
FLASH
Program Memory Size
128KB (64K x 16)
Package / Case
80-TFQFP
Core Processor
PIC
Core Size
8-Bit
Speed
25MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
68
Eeprom Size
1K x 8
Ram Size
3.75K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3.75 KB
Interface Type
I2C/SPI/USART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
68
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DM183032, DM183022, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
16-ch x 10-bit
Package
80TQFP
Device Core
PIC
Family Name
PIC18
Maximum Speed
25 MHz
Operating Supply Voltage
5 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT80PT3 - SOCKET TRAN ICE 80MQFP/TQFPAC164320 - MODULE SKT MPLAB PM3 80TQFPAC174011 - MODULE SKT PROMATEII 80TQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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PIC18F6520/8520/6620/8620/6720/8720
18.2.2
The USART receiver block diagram is shown in
Figure 18-4. The data is received on the pin (RC7/RX1/
DT1 or RG2/RX2/DT2) and drives the data recovery
block. The data recovery block is actually a high-speed
shifter operating at 16 times the baud rate, whereas the
main receive serial shifter operates at the bit rate or at
F
systems.
To set up an Asynchronous Reception:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. If using interrupts, ensure that the GIE and PEIE
FIGURE 18-4:
DS39609B-page 206
OSC
Initialize the SPBRG register for the appropriate
baud rate. If a high-speed baud rate is desired,
set bit BRGH (Section 18.1 “USART Baud
Rate Generator (BRG)”).
Enable the asynchronous serial port by clearing
bit SYNC and setting bit SPEN.
If interrupts are desired, set enable bit RCxIE.
If 9-bit reception is desired, set bit RX9.
Enable the reception by setting bit CREN.
Flag bit RCxIF will be set when reception is com-
plete and an interrupt will be generated if enable
bit RCxIE was set.
Read the RCSTAx register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
Read the 8-bit received data by reading the
RCREG register.
If any error occurred, clear the error by clearing
enable bit CREN.
bits in the INTCON register (INTCON<7:6>) are
set.
. This mode would typically be used in RS-232
USART ASYNCHRONOUS
RECEIVER
RX pin
Baud Rate Generator
x64 Baud Rate CLK
USART RECEIVE BLOCK DIAGRAM
SPBRG
and Control
Pin Buffer
SPEN
Recovery
Interrupt
Data
or
64
16
CREN
18.2.3
This mode would typically be used in RS-485 systems.
To set up an Asynchronous Reception with Address
Detect Enable:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. If any error occurred, clear the CREN bit.
11. If the device has been addressed, clear the
RX9
Initialize the SPBRGx register for the appropri-
ate baud rate. If a high-speed baud rate is
required, set the BRGH bit.
Enable the asynchronous serial port by clearing
the SYNC bit and setting the SPEN bit.
If interrupts are required, set the RCEN bit and
select the desired priority level with the RCIP bit.
Set the RX9 bit to enable 9-bit reception.
Set the ADDEN bit to enable address detect.
Enable reception by setting the CREN bit.
The RCxIF bit will be set when reception is
complete. The interrupt will be Acknowledged if
the RCxIE and GIE bits are set.
Read the RCSTAx register to determine if any
error occurred during reception, as well as read
bit 9 of data (if applicable).
Read RCREGx to determine if the device is
being addressed.
ADDEN bit to allow all received data into the
receive buffer and interrupt the CPU.
Stop
MSb
RCIF
RCIE
RX9D
(8)
SETTING UP 9-BIT MODE WITH
ADDRESS DETECT
OERR
7
RSR Register
RCREG Register
8
Data Bus
 2004 Microchip Technology Inc.
1
FERR
0
LSb
Start
FIFO

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