LPC3250FET296/01,5 NXP Semiconductors, LPC3250FET296/01,5 Datasheet - Page 53

• Manufacturer Part Number: LPC3250FET296/01,5
• Description: IC ARM9 MCU 256K 296-TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC32x0r

Specifications of LPC3250FET296/01,5

• Package / Case: 296-TFBGA
• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 266MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, Motor Control PWM, PWM, WDT
• Number Of I /o: 51
• Program Memory Type: ROMless
• Ram Size: 256K x 8
• Voltage - Supply (vcc/vdd): 0.9 V ~ 3.6 V
• Data Converters: A/D 3x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC32
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 256 KB
• Interface Type: EMC
• Maximum Clock Frequency: 266 MHz
• Number Of Timers: 6
• Operating Supply Voltage: 1.31 V to 1.39 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, DK-57TS-LPC3250, DK-57VTS-LPC3250, SOMDIMM-LPC3250
• Development Tools By Supplier: OM11016, OM11021, OM11045
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 3 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4962; 935290766551

NXP Semiconductors
Table 11.
T
[1]
[2]
[3]
[4]
[5]
[6]
LPC3220_30_40_50_1
Preliminary data sheet
Symbol
f
t
t
t
t
t
t
t
t
t
t
t
t
oper
CK
CL
CH
d(V)ctrl
h(ctrl)
d(AV)
h(A)
d(QV)
h(Q)
su(D)
h(D)
QZ
amb
Parameters are valid over operating temperature range unless otherwise specified.
Typical values valid for EMC pads set to high slew rate: VDD_EMC = 1.8 V, VDD_CORE = 1.2 V or low slew rate: VDD_EMC = 3.3 V,
VDD_CORE = 1.2 V.
All min or max values valid for EMC pads set to high slew rate: VDD_EMC = 1.8 V, VDD_CORE = 1.2 V or low slew rate: VDD_EMC =
3.3 V, VDD_CORE = 1.2 V.
f
Applies to signals: EMC_DQM[3:0], EMC_DYCSm, EMC_RAS, EMC_CAS, EMC_WR, EMC_CKEm.
CMD_DLY = COMMAND_DELAY bitfield in SDRAMCLK_CTRL[18:14] register, see External memory controller (EMC) chapter in
LPC32x0 User manual .
oper
= 40 C to +85 C, unless otherwise specified.
= 1/t
EMC SDR SDRAM memory interface dynamic characteristics
Parameter
operating frequency
clock cycle time
CK LOW-level width
CK HIGH-level width
control valid delay time
control hold time
address valid delay time
address hold time
data output valid delay time
data output hold time
data input set-up time
data input hold time
data output high-impedance time
CK.
11.3 SDR SDRAM Controller
11.4 DDR SDRAM controller
Fig 7.
SDR SDRAM signal timing
output signal (O)
input signal (I)
EMC_CLK
Rev. 01 — 6 February 2009
[5][6]
[5][6]
[1][3]
[4]
[6]
[6]
[6]
[6]
Min
-
-
-
-
-
-
-
-
-
t
d(V)ctrl
, t
Typical
104
9.6
4.8
4.8
(CMD_DLY
(CMD_DLY
(CMD_DLY
(CMD_DLY
(CMD_DLY
(CMD_DLY
0.6
0.9
-
t
d(AV)
CH
, t
d(QV)
[2]
t
CK
LPC3220/30/40/50
0.25) + 2.7
0.25) + 1.2
0.25) + 3.2
0.25) + 1.2
0.25) + 3.5
0.25) + 1.2
t
CL
t
su(D)
16/32-bit ARM microcontrollers
t
t
h(D)
h(ctrl)
, t
t
002aae420
Max
133
-
-
-
-
-
-
-
-
QZ
h(Q)
t
CK
, t
h(A)
© NXP B.V. 2009. All rights reserved.
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
53 of 73