LPC3250FET296/01,5 NXP Semiconductors, LPC3250FET296/01,5 Datasheet - Page 65

• Manufacturer Part Number: LPC3250FET296/01,5
• Description: IC ARM9 MCU 256K 296-TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC32x0r

Specifications of LPC3250FET296/01,5

• Package / Case: 296-TFBGA
• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 266MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, Motor Control PWM, PWM, WDT
• Number Of I /o: 51
• Program Memory Type: ROMless
• Ram Size: 256K x 8
• Voltage - Supply (vcc/vdd): 0.9 V ~ 3.6 V
• Data Converters: A/D 3x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC32
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 256 KB
• Interface Type: EMC
• Maximum Clock Frequency: 266 MHz
• Number Of Timers: 6
• Operating Supply Voltage: 1.31 V to 1.39 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, DK-57TS-LPC3250, DK-57VTS-LPC3250, SOMDIMM-LPC3250
• Development Tools By Supplier: OM11016, OM11021, OM11045
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 3 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4962; 935290766551

NXP Semiconductors
Table 19.
T
LPC3220_30_40_50_1
Preliminary data sheet
Symbol
SSP 0 in SPI master mode
T
t
t
t
t
t
t
SSP 1 in SPI master mode
T
t
t
t
t
t
t
SSP0 in SPI slave mode
t
t
t
t
SSP1 in SPI slave mode
t
t
t
t
SPICLKH
SPICLKL
SPIDSU
SPIDH
SPIQV
SPIOH
SPICLKH
SPICLKL
SPIDSU
SPIDH
SPIQV
SPIOH
SPIDSU
SPIDH
SPIQV
SPIOH
SPIDSU
SPIDH
SPIQV
SPIOH
amb
SPICYC
SPICYC
= 40 C to +85 C.
Dynamic characteristics of SSP controller pins in SPI mode
11.10.2 SSP
Parameter
SPI cycle time
SPICLK HIGH time
SPICLK LOW time
SPI data set-up time
SPI data hold time
SPI data output valid time
SPI output data hold time
SPI cycle time
SPICLK HIGH time
SPICLK LOW time
SPI data set-up time
SPI data hold time
SPI data output valid time
SPI output data hold time
SPI data set-up time
SPI data hold time
SPI data output valid time
SPI output data hold time
SPI data set-up time
SPI data hold time
SPI data output valid time
SPI output data hold time
Rev. 01 — 6 February 2009
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© NXP B.V. 2009. All rights reserved.
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