LPC3250FET296/01,5 NXP Semiconductors, LPC3250FET296/01,5 Datasheet - Page 55

• Manufacturer Part Number: LPC3250FET296/01,5
• Description: IC ARM9 MCU 256K 296-TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC32x0r

Specifications of LPC3250FET296/01,5

• Package / Case: 296-TFBGA
• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 266MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, Motor Control PWM, PWM, WDT
• Number Of I /o: 51
• Program Memory Type: ROMless
• Ram Size: 256K x 8
• Voltage - Supply (vcc/vdd): 0.9 V ~ 3.6 V
• Data Converters: A/D 3x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC32
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 256 KB
• Interface Type: EMC
• Maximum Clock Frequency: 266 MHz
• Number Of Timers: 6
• Operating Supply Voltage: 1.31 V to 1.39 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, DK-57TS-LPC3250, DK-57VTS-LPC3250, SOMDIMM-LPC3250
• Development Tools By Supplier: OM11016, OM11021, OM11045
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 3 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4962; 935290766551

NXP Semiconductors
LPC3220_30_40_50_1
Preliminary data sheet
Fig 8.
Fig 9.
Fig 10. DDR read timing parameters
(1) The delay of the EMC_DQSm signal is determined by the DQS_DELAY settings. See LPC32x0 user manual, External Memory
DDR control timing parameters
DDR write timing parameters
Controller Chapter, section DDR DQS delay calibration for details on configuring this value.
delayed EMC_DQSm
EMC_DQM[1:0]
EMC_D[31:0],
EMC_D[31:0]
EMC_DQSm
EMC_DQSm
EMC_CLK
EMC_CLK
command
command
EMC control
(1)
and address
EMC_CLK
signals
READ
WRITE
t
d(AV);
t
WPRE
t
Rev. 01 — 6 February 2009
DQSS
t
d(V)ctrl
t
CK
t
RPRE
t
su(D)
t
valid
t
DQSL
DSS
t
t
su(Q)
h(A);
t
t
h(ctl)
CH
t
h(Q)
t
t
DQSH
DSH
t
d(DQS)
LPC3220/30/40/50
t
WPST
t
CL
16/32-bit ARM microcontrollers
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t
RPST
002aae437
© NXP B.V. 2009. All rights reserved.
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