Z8F0411HH020SG Zilog, Z8F0411HH020SG Datasheet - Page 145
Z8F0411HH020SG
Manufacturer Part Number
Z8F0411HH020SG
Description
IC ENCORE MCU FLASH 4K 20SSOP
Manufacturer
Zilog
Series
Encore!® XP®r
Specifications of Z8F0411HH020SG
Core Processor
Z8
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, IrDA, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
11
Program Memory Size
4KB (4K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
20-SSOP
Controller Family/series
Z8
No. Of I/o's
11
Ram Memory Size
1KB
Cpu Speed
20MHz
No. Of Timers
2
Rohs Compliant
Yes
Processor Series
Z8F041xx
Core
eZ8
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
I2C, UART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
11
Number Of Timers
2
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
0 C
For Use With
770-1002 - ISP 4PORT ZILOG Z8 ENCORE! MCU269-4643 - KIT DEV Z8 ENCORE XP 28-PIN269-4630 - DEV KIT FOR Z8 ENCORE 8K/4K269-4629 - KIT DEV Z8 ENCORE XP 28-PIN269-4628 - KIT DEV Z8 ENCORE XP 8-PIN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
Other names
269-4101
Z8F0411HH020SG
Z8F0411HH020SG
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
Z8F0411HH020SG
Manufacturer:
Zilog
Quantity:
68
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PS022517-0508
Write Transaction with a 7-Bit Address
Figure 27
indicate data transferred from the I
data transferred from the slaves to the I
Follow the steps below for a transmit operation to a 7-bit addressed slave:
1. Software asserts the IEN bit in the I
2. Software asserts the TXI bit of the I
3. The I
4. Software responds to the TDRE bit by writing a 7-bit Slave address plus write bit (=0)
5. Software asserts the START bit of the I
6. The I
7. The I
8. After one bit of address has been shifted out by the SDA signal, the Transmit Interrupt
9. Software responds by writing the transmit data into the I
10. The I
11. If the I
12. The I
13. The I
S
to the I
Register.
is asserted (TDRE = 1).
next high period of SCL the I
Continue with
If the slave does not acknowledge, the Not Acknowledge interrupt occurs (NCKI bit is
set in the Status register, ACK bit is cleared). Software responds to the Not
Acknowledge interrupt by setting the STOP and FLUSH bits and clearing the TXI bit.
The I
NCKI bits. The transaction is complete (ignore following steps).
I
sent, the Transmit Interrupt is asserted.
2
C Data Register.
Slave Address
2
2
2
2
2
2
2
displays the data transfer format for a 7-bit addressed slave. Shaded regions
C interrupt asserts, because the I
C Controller sends the START condition to the I
C Controller loads the I
C Controller shifts the rest of the address and write bit out by the SDA signal.
C Controller sends the STOP condition on the bus and clears the STOP and
C Controller loads the contents of the I
C Controller shifts the data out of using the SDA signal. After the first bit is
2
2
C Slave sends an acknowledge (by pulling the SDA signal low) during the
C Data Register.
Figure 27. 7-Bit Addressed Slave Data Transfer Format
step
12.
W = 0
A
2
2
C Controller sets the ACK bit in the I
2
C Shift register with the contents of the I
C Controller to slaves and unshaded regions indicate
2
2
C Controller.
Data
2
C Control Register.
C Control Register to enable Transmit Interrupts.
2
2
C Data Register is empty.
C Control Register.
2
A
C Shift register with the contents of the
Z8 Encore! XP
Data
2
C Slave.
2
C Data Register.
Product Specification
A
Data
2
C Status register.
®
F0822 Series
2
C Data
I2C Controller
A/A P/S
132
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