Z8F0411HH020SG Zilog, Z8F0411HH020SG Datasheet - Page 63
Z8F0411HH020SG
Manufacturer Part Number
Z8F0411HH020SG
Description
IC ENCORE MCU FLASH 4K 20SSOP
Manufacturer
Zilog
Series
Encore!® XP®r
Specifications of Z8F0411HH020SG
Core Processor
Z8
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, IrDA, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
11
Program Memory Size
4KB (4K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
20-SSOP
Controller Family/series
Z8
No. Of I/o's
11
Ram Memory Size
1KB
Cpu Speed
20MHz
No. Of Timers
2
Rohs Compliant
Yes
Processor Series
Z8F041xx
Core
eZ8
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
I2C, UART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
11
Number Of Timers
2
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
0 C
For Use With
770-1002 - ISP 4PORT ZILOG Z8 ENCORE! MCU269-4643 - KIT DEV Z8 ENCORE XP 28-PIN269-4630 - DEV KIT FOR Z8 ENCORE 8K/4K269-4629 - KIT DEV Z8 ENCORE XP 28-PIN269-4628 - KIT DEV Z8 ENCORE XP 8-PIN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
Other names
269-4101
Z8F0411HH020SG
Z8F0411HH020SG
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
Z8F0411HH020SG
Manufacturer:
Zilog
Quantity:
68
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Table 14. Port A–C GPIO Address Registers (PxADDR)
PS022517-0508
BITS
FIELD
RESET
R/W
ADDR
Port A–C Address Registers
7
Table 13. GPIO Port Registers and Sub-Registers (Continued)
The Port A–C Address Registers select the GPIO Port functionality accessible through
the Port A–C Control Registers. The Port A–C Address and Control Registers combine to
provide access to all GPIO Port control
PADDR[7:0]—Port Address
The Port Address selects one of the sub-registers accessible through the Port Control
register.
Port Register Mnemonic
PxOC
PxHDE
PxSMRE
PxPUE
PADDR[7:0]
00H
01H
02H
03H
04H
05H
06H
07H–FFH
6
5
Port Control Sub-Register Accessible Using the Port A–C
Control Registers
No function. Provides some protection against accidental
Port reconfiguration.
Data Direction
Alternate Function
Output Control (Open-Drain)
High Drive Enable
Stop Mode Recovery Source Enable
Pull-up Enable
No Function
4
FD0H, FD4H, FD8H
Port Register Name
Output Control (Open-Drain)
High Drive Enable
Stop Mode Recovery Source Enable
Pull-up Enable
PADDR[7:0]
(Table
R/W
00H
3
14).
2
Z8 Encore! XP
General-Purpose Input/Output
Product Specification
1
®
F0822 Series
0
50
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