Z8F0411HH020SG Zilog, Z8F0411HH020SG Datasheet - Page 72

• Manufacturer Part Number: Z8F0411HH020SG
• Description: IC ENCORE MCU FLASH 4K 20SSOP
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F0411HH020SG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 11
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 20-SSOP
• Controller Family/series: Z8
• No. Of I/o's: 11
• Ram Memory Size: 1KB
• Cpu Speed: 20MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• Processor Series: Z8F041xx
• Core: eZ8
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 11
• Number Of Timers: 2
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• For Use With: 770-1002 - ISP 4PORT ZILOG Z8 ENCORE! MCU269-4643 - KIT DEV Z8 ENCORE XP 28-PIN269-4630 - DEV KIT FOR Z8 ENCORE 8K/4K269-4629 - KIT DEV Z8 ENCORE XP 28-PIN269-4628 - KIT DEV Z8 ENCORE XP 8-PIN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4101; Z8F0411HH020SG

Architecture
Operation
PS022517-0508
Master Interrupt Enable
Figure 9
The master interrupt enable bit (IRQE) in the Interrupt Control Register globally enables
and disables interrupts.
Interrupts are globally enabled by any of the following actions:
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•
•
Interrupts are globally disabled by any of the following actions:
•
•
•
•
•
•
Internal Interrupts
Port Interrupts
Execution of an
Execution of an
Writing a 1 to the IRQE bit in the Interrupt Control Register.
Execution of a
eZ8 CPU acknowledgement of an interrupt service request from the interrupt controller.
Writing a 0 to the IRQE bit in the Interrupt Control Register.
Reset.
Execution of a Trap instruction.
Illegal Instruction trap.
displays a block diagram of the interrupt controller.
DI
Figure 9. Interrupt Controller Block Diagram
EI
IRET
(Disable Interrupt) instruction.
(Enable Interrupt) instruction.
(Return from Interrupt) instruction.
Medium
Priority
Priority
Priority
High
Low
Priority
Z8 Encore! XP
Mux
Vector
IRQ Request
Product Specification
®
Interrupt Controller
F0822 Series
59