Z8F0411HH020SG Zilog, Z8F0411HH020SG Datasheet - Page 152
Z8F0411HH020SG
Manufacturer Part Number
Z8F0411HH020SG
Description
IC ENCORE MCU FLASH 4K 20SSOP
Manufacturer
Zilog
Series
Encore!® XP®r
Specifications of Z8F0411HH020SG
Core Processor
Z8
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, IrDA, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
11
Program Memory Size
4KB (4K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
20-SSOP
Controller Family/series
Z8
No. Of I/o's
11
Ram Memory Size
1KB
Cpu Speed
20MHz
No. Of Timers
2
Rohs Compliant
Yes
Processor Series
Z8F041xx
Core
eZ8
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
I2C, UART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
11
Number Of Timers
2
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
0 C
For Use With
770-1002 - ISP 4PORT ZILOG Z8 ENCORE! MCU269-4643 - KIT DEV Z8 ENCORE XP 28-PIN269-4630 - DEV KIT FOR Z8 ENCORE 8K/4K269-4629 - KIT DEV Z8 ENCORE XP 28-PIN269-4628 - KIT DEV Z8 ENCORE XP 8-PIN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
Other names
269-4101
Z8F0411HH020SG
Z8F0411HH020SG
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
Z8F0411HH020SG
Manufacturer:
Zilog
Quantity:
68
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Table 70. I
I
PS022517-0508
BITS
FIELD
RESET
R/W
ADDR
2
C Control Register Definitions
I
2
C Data Register
2
C Data Register (I2CDATA)
7
19. The I
20. The I
21. Software responds by reading the I
22. If there are one or more bytes to transfer, return to
23. After the last byte is shifted in, a Not Acknowledge interrupt is generated by the I
24. Software responds by setting the STOP bit of the I
25. A STOP condition is sent to the I
The I
ister during a write to a slave. This register also holds data that is loaded from the I
register during a read from a slave. The I
File address space, but is used only to buffer incoming and outgoing data.
STOP condition on the bus and clears the STOP and NCKI bits. The transaction is
complete (ignore the following steps).
I
byte), else it sends an Acknowledge.
there is only one more byte to receive, set the NAK bit of the I
Controller.
2
2
C Controller sends a Not Acknowledge to the I
C Data Register
2
2
C Controller shifts in a byte of data from the I
C Controller asserts the Receive interrupt (RDRF bit set in the Status register).
6
(Table
5
70) holds the data that is to be loaded into the I
4
2
C Slave and the STOP and NCKI bits are cleared.
2
DATA
F50H
C Data Register which clears the RDRF bit. If
R/W
2
C Shift Register is not accessible in the Register
0
3
2
C Slave if the NAK bit is set (last
2
step
C Control Register.
Z8 Encore! XP
2
C Slave on the SDA signal. The
19.
2
Product Specification
2
C Control Register.
1
®
F0822 Series
2
I2C Controller
C Shift reg-
2
C Shift
0
2
C
139
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