R5F21102DFP#U0 Renesas Electronics America, R5F21102DFP#U0 Datasheet - Page 109

• Manufacturer Part Number: R5F21102DFP#U0
• Description: IC R8C MCU FLASH 8K 32LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/R8C/Tiny/10r

Specifications of R5F21102DFP#U0

• Core Processor: R8C
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: SIO, UART/USART
• Peripherals: LED, WDT
• Number Of I /o: 22
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• For Use With: R0K521134S000BE - KIT EVAL STARTER FOR R8C/13R0E521134EPB00 - KIT EMULATOR PROBE FOR PC7501R0E521134CPE00 - EMULATOR COMPACT R8C/13
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/10 Group
Rev.1.20 Jan 27, 2006
REJ09B0019-0120
Figure 13.7 Transfer Clock Polarity
Figure 13.8 Transfer Format
13.1.1 Polarity Select Function
13.1.2 LSB First/MSB First Select Function
Figure 13.7 shows the polarity of the transfer clock. Use the CKPOL bit in the U0C0 register to select
the transfer clock polarity.
Figure 13.8 shows the transfer format. Use the UFORM bit in the U0C0 register to select the transfer
format.
page 97 of 180
R
R
NOTES:
( 1 ) W h e n t h e U 0 C 0 r e g i s t e r C K P O L b i t = 0 ( t r a n s m i t d a t a o u t p u t a t t h e f a l l i n g
C L K
T
C L K
T
( 2 ) W h e n t h e U 0 C 0 r e g i s t e r C K P O L b i t = 1 ( t r a n s m i t d a t a o u t p u t a t t h e r i s i n g
( 1 ) W h e n U 0 C 0 r e g i s t e r U F O R M b i t = 0 ( L S B f i r s t )
( 2 ) W h e n U 0 C 0 r e g i s t e r U F O R M b i t = 1 ( M S B f i r s t )
1. When not transferring, the CLK0 pin outputs a high signal.
2. When not transferring, the CLK0 pin outputs a low signal.
C L K
T
R
C L K
T
R
N O T E S :
X
X
X
X
D
D
X
X
D
D
X
X
1 . T h i s a p p l i e s t o t h e c a s e w h e r e t h e C K P O L b i t i n t h e U 0 C 0 r e g i s t e r i s
e d g e a n d t h e r e c e i v e d a t a t a k e n i n a t t h e r i s i n g e d g e o f t h e t r a n s f e r c l o c k )
e d g e a n d t h e r e c e i v e d a t a t a k e n i n a t t h e f a l l i n g e d g e o f t h e t r a n s f e r c l o c k )
D
D
0
0
D
D
0
0
0
0
( 1 )
( 2 )
0
0
0
0
0
0
s e t t o “ 0 ” ( t r a n s m i t d a t a o u t p u t a t t h e f a l l i n g e d g e a n d t h e r e c e i v e
d a t a t a k e n i n a t t h e r i s i n g e d g e o f t h e t r a n s f e r c l o c k ) .
D 0
D
D
D
D 0
D
D
D
0
0
0
0
7
7
D
D
D
D
D
D
D
D
1
1
1
1
1
6
1
6
D
D
D
D
D
D
D
D
2
2
2
2
2
5
2
5
D
D
D
D
D
D
D
D
3
3
3
3
3
3
4
4
D
D
D
D
D
D
D
D
4
4
4
4
4
4
3
3
D
D
D
D
D
D
D
D
5
5
5
5
13.1 Clock Synchronous Serial I/O Mode
5
5
2
2
D
D
D
D
D
D
D
D
6
6
6
6
6
1
6
1
D
D
D
D
D
D
D
D
7
7
7
7
7
7
0
0