R5F21102DFP#U0 Renesas Electronics America, R5F21102DFP#U0 Datasheet - Page 162

IC R8C MCU FLASH 8K 32LQFP

R5F21102DFP#U0

Manufacturer Part Number
R5F21102DFP#U0
Description
IC R8C MCU FLASH 8K 32LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/R8C/Tiny/10r
Datasheets

Specifications of R5F21102DFP#U0

Core Processor
R8C
Core Size
16-Bit
Speed
16MHz
Connectivity
SIO, UART/USART
Peripherals
LED, WDT
Number Of I /o
22
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-LQFP
For Use With
R0K521134S000BE - KIT EVAL STARTER FOR R8C/13R0E521134EPB00 - KIT EMULATOR PROBE FOR PC7501R0E521134CPE00 - EMULATOR COMPACT R8C/13
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R5F21102DFP#U0
Manufacturer:
Renesas Electronics America
Quantity:
10 000
R8C/10 Group
Rev.1.20 Jan 27, 2006
REJ09B0019-0120
Table 17.4 Software Commands
SRD: Status register data (D
WA: Write address (Make sure the address value specified in the the first bus cycle is the same address
WD: Write data (8 bits)
BA: Given block address
X: Any address in the user ROM area
Read array
Read status register
Clear status register
Block erase
Program
17.4.3 Software Commands
as the write address specified in the second bus cycle.)
Software commands are described below. The command code and data must be read and written in
8-bit units.
• Read Array Command
• Read Status Register Command
• Clear Status Register Command
This command reads the flash memory.
Writing ‘FF
address in the next or subsequent bus cycles, and the content of the specified address can be read
in 8-bit units.
Because the microcomputer remains in read array mode until another command is written, the con-
tents of multiple addresses can be read in succession.
This command reads the status register.
Write ‘70
to Section 17.4.4, “Status Register.”) When reading the status register too, specify an address in the
user ROM area.
Avoid executing this command in EW1 mode.
This command sets the status register to “0”.
Write ‘50
in the status register will be set to “0”.
Command
16
16
’ in the first bus cycle, and the FMR06 to FMR07 bits in the FMR0 register and SR4 to SR5
’ in the first bus cycle, and the status register can be read in the second bus cycle. (Refer
16
page 150 of 180
’ in the first bus cycle places the microcomputer in read array mode. Enter the read
7
to D
Write
Write
Write
Write
Write
Mode
0
)
First bus cycle
Address
WA
X
X
X
X
(D
7
Data
FF
70
50
40
20
to D
16
16
16
16
16
0
)
Mode
Read
Write
Write
Second bus cycle
Address
17.4 CPU Rewrite Mode
WA
BA
X
(D
SRD
D0
7
WD
Data
to D
16
0
)

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