C8051F702-GQ Silicon Laboratories Inc, C8051F702-GQ Datasheet - Page 180

• Manufacturer Part Number: C8051F702-GQ
• Description: IC 8051 MCU 16K FLASH 64-TQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F70xr

Specifications of C8051F702-GQ

• Program Memory Type: FLASH
• Program Memory Size: 16KB (16K x 8)
• Package / Case: 64-TQFP, 64-VQFP
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Cap Sense, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 54
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: C8051F7x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 54
• Number Of Timers: 4 x 16 bit
• Operating Supply Voltage: 1.8 V to 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F700DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 336-1635 - DEV KIT FOR C8051F700
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1608

C8051F70x/71x
28. Port Input/Output
Digital and analog resources are available through 64 I/O pins. Each of the Port pins P0.0–P2.7 can be
defined as general-purpose I/O (GPIO), assigned to one of the internal digital resources, or assigned to an
analog function as shown in Figure 28.4. The designer has complete control over which functions are
assigned, limited only by the number of physical I/O pins. This resource assignment flexibility is achieved
through the use of a Priority Crossbar Decoder. The state of a Port I/O pin can always be read in the corre-
sponding Port latch, regardless of the Crossbar settings.
The Crossbar assigns the selected internal digital resources to the I/O pins based on the Priority Decoder.
The registers XBR0 and XBR1, defined in SFR Definition 28.1 and SFR Definition 28.2, are used to select
internal digital functions.
All Port I/Os except P0.3 are tolerant of voltages up to 2 V above the V
the Port cell circuit). The Port I/O cells are configured as either push-pull or open-drain in the Port Output
Mode registers (PnMDOUT, where n = 0,1). Complete Electrical Specifications for Port I/O are given in
Section “9. Electrical Characteristics” on page 47.
180
H ighest
P riority
Low est
P riority
S Y SC LK
O utputs
SM Bus
T0, T1
U AR T
P 0
P 1
PC A
C P0
S PI
(P0.0-P 0.7)
(P1.0-P 1.7)
Figure 28.1. Port I/O Functional Block Diagram
2
4
2
2
4
2
8
8
(A D C 0, C P0, V R E F, XTAL)
To Analog Peripherals
Rev. 1.0
P nS K IP R egisters
X BR 0, XB R1,
C rossbar
Decoder
Priority
Digital
To C S0
8
8
8
P 0M AS K , P0M A T
P 1M AS K , P1M A T
Port M atch
DD
C ells
C ells
C ells
C ells
C ells
C ells
C ells
supply (refer to Figure 28.2 for
I/O
I/O
I/O
I/O
I/O
I/O
P1
I/O
P 2
P3
P4
P5
P 6
P0
External Interrupts
PnM D IN , P nD R V
EX0 and E X1
PnM D O U T,
R egisters
P4.0
P4.7
P5.0
P5.7
P0.0
P0.7
P1.0
P1.7
P2.0
P2.7
P3.0
P3.7
P6.0
P6.5