C8051F702-GQ Silicon Laboratories Inc, C8051F702-GQ Datasheet - Page 248

• Manufacturer Part Number: C8051F702-GQ
• Description: IC 8051 MCU 16K FLASH 64-TQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F70xr

Specifications of C8051F702-GQ

• Program Memory Type: FLASH
• Program Memory Size: 16KB (16K x 8)
• Package / Case: 64-TQFP, 64-VQFP
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Cap Sense, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 54
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: C8051F7x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 54
• Number Of Timers: 4 x 16 bit
• Operating Supply Voltage: 1.8 V to 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F700DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 336-1635 - DEV KIT FOR C8051F700
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1608

C8051F70x/71x
SFR Definition 31.1. SPI0CFG: SPI0 Configuration
SFR Address = 0xA1; SFR Page = 0
248
Note: In slave mode, data on MOSI is sampled in the center of each data bit. In master mode, data on MISO is
Name
Reset
Bit
Type
7
6
5
4
3
2
1
0
Bit
sampled one SYSCLK before the end of each data bit, to provide maximum settling time for the slave device.
See Table 31.1 for timing parameters.
SLVSEL
SPIBSY
MSTEN
RXBMT
CKPHA
CKPOL
SPIBSY
NSSIN
SRMT
Name
R
7
0
MSTEN
SPI Busy.
This bit is set to logic 1 when a SPI transfer is in progress (master or slave mode).
Master Mode Enable.
0: Disable master mode. Operate in slave mode.
1: Enable master mode. Operate as a master.
SPI0 Clock Phase.
0: Data centered on first edge of SCK period.
1: Data centered on second edge of SCK period.
SPI0 Clock Polarity.
0: SCK line low in idle state.
1: SCK line high in idle state.
Slave Selected Flag.
This bit is set to logic 1 whenever the NSS pin is low indicating SPI0 is the selected
slave. It is cleared to logic 0 when NSS is high (slave not selected). This bit does
not indicate the instantaneous value at the NSS pin, but rather a de-glitched ver-
sion of the pin input.
NSS Instantaneous Pin Input.
This bit mimics the instantaneous value that is present on the NSS port pin at the
time that the register is read. This input is not de-glitched.
Shift Register Empty (valid in slave mode only).
This bit will be set to logic 1 when all data has been transferred in/out of the shift
register, and there is no new information available to read from the transmit buffer
or write to the receive buffer. It returns to logic 0 when a data byte is transferred to
the shift register from the transmit buffer or by a transition on SCK. SRMT = 1 when
in Master Mode.
Receive Buffer Empty (valid in slave mode only).
This bit will be set to logic 1 when the receive buffer has been read and contains no
new information. If there is new information available in the receive buffer that has
not been read, this bit will return to logic 0. RXBMT = 1 when in Master Mode.
R/W
6
0
CKPHA
R/W
5
0
CKPOL
R/W
Rev. 1.0
4
0
SLVSEL
Function
R
3
0
*
NSSIN
*
R
2
1
SRMT
R
1
1
RXBMT
R
0
1