C8051F702-GQ Silicon Laboratories Inc, C8051F702-GQ Datasheet - Page 305

• Manufacturer Part Number: C8051F702-GQ
• Description: IC 8051 MCU 16K FLASH 64-TQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F70xr

Specifications of C8051F702-GQ

• Program Memory Type: FLASH
• Program Memory Size: 16KB (16K x 8)
• Package / Case: 64-TQFP, 64-VQFP
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Cap Sense, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 54
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: C8051F7x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 54
• Number Of Timers: 4 x 16 bit
• Operating Supply Voltage: 1.8 V to 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F700DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 336-1635 - DEV KIT FOR C8051F700
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1608

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Revision 0.3 to Revision 0.4
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Revision 0.2 to Revision 0.3
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OCUMENT
Updated “Electrical Characteristics” on page 47.
Updated “Port Input/Output” on page 180.
Removed Incorrect Pin Connections in Figure 1.4 on page 21 and Figure 1.6 on page 23.
Updated Specifications in Section “9. Electrical Characteristics” on page 47.
Updated Section “15. Capacitive Sense (CS0)” on page 80 for clarity.
Corrected “CJNE A, direct, rel” instruction timing in Table 16.1.
Noted that a minimum SYSCLK speed is required for Flash writes or erases in Section
“22.1. Programming The Flash Memory” on page 148, and for EEPROM writes in Section
“23.3. Interfacing with the EEPROM” on page 155.
Corrected P0.3 overvoltage capabilities throughout document.
Updated Section “15. Capacitive Sense (CS0)” on page 80 to reflect Revision B enhancements.
Added C8051F716 and C8051F717 devices, package information, and features.
Updated Register 19.1, “HWID: Hardware Identification Byte,” on page 128.
Corrected minor typographical and formatting errors throughout document.
Corrected Dimension D in the QFN-48 Package Specifications.
Updated Table 9.1 on page 47.
Updated Register 10.1, “ADC0CF: ADC0 Configuration,” on page 59.
Updated Register 14.3, “CPT0MX: Comparator0 MUX Selection,” on page 79.
Updated Section “28.1.1. Port Pins Configured for Analog I/O” on page 181.
Updated Register 35.2, “DEVICEID: C2 Device ID,” on page 302.
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