C8051F702-GQ Silicon Laboratories Inc, C8051F702-GQ Datasheet - Page 74

• Manufacturer Part Number: C8051F702-GQ
• Description: IC 8051 MCU 16K FLASH 64-TQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F70xr

Specifications of C8051F702-GQ

• Program Memory Type: FLASH
• Program Memory Size: 16KB (16K x 8)
• Package / Case: 64-TQFP, 64-VQFP
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Cap Sense, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 54
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: C8051F7x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 54
• Number Of Timers: 4 x 16 bit
• Operating Supply Voltage: 1.8 V to 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F700DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 336-1635 - DEV KIT FOR C8051F700
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1608

C8051F70x/71x
14. Comparator0
C8051F70x/71x devices include an on-chip programmable voltage comparator, Comparator0, shown in
Figure 14.1.
The Comparator offers programmable response time and hysteresis, an analog input multiplexer, and two
outputs that are optionally available at the Port pins: a synchronous “latched” output (CP0), or an asyn-
chronous “raw” output (CP0A). The asynchronous CP0A signal is available even when the system clock is
not active. This allows the Comparator to operate and generate an output with the device in STOP mode.
When assigned to a Port pin, the Comparator output may be configured as open drain or push-pull (see
Section “28.4. Port I/O Initialization” on page 189). Comparator0 may also be used as a reset source (see
Section “25.5. Comparator0 Reset” on page 167).
The Comparator0 inputs are selected by the comparator input multiplexer, as detailed in Section
“14.1. Comparator Multiplexer” on page 78.
The Comparator output can be polled in software, used as an interrupt source, and/or routed to a Port pin.
When routed to a Port pin, the Comparator output is available asynchronous or synchronous to the system
clock; the asynchronous output is available even in STOP mode (with no system clock active). When dis-
abled, the Comparator output (if assigned to a Port I/O pin via the Crossbar) defaults to the logic low state,
and the power supply to the comparator is turned off. See Section “28.3. Priority Crossbar Decoder” on
page 185 for details on configuring Comparator outputs via the digital Crossbar. Comparator inputs can be
externally driven from –0.25 V to (V
trical specifications are given in Section “9. Electrical Characteristics” on page 47.
74
Comparator
Input Mux
Figure 14.1. Comparator0 Functional Block Diagram
CPT0MD
CP0 +
CP0 -
DD
+
-
) + 0.25 V without damage or upset. The complete Comparator elec-
CPT0CN
VDD
GND
CP0RIF
CP0FIF
Decision
Reset
Tree
Rev. 1.0
(SYNCHRONIZER)
D
SET
CLR
Q
Q
0
1
0
1
D
SET
CLR
Q
Q
CP0EN
Crossbar
0
1
EA
0
1
CP0A
Interrupt
CP0
CP0