MC9S12E64CFUE Freescale Semiconductor, MC9S12E64CFUE Datasheet - Page 241

• Manufacturer Part Number: MC9S12E64CFUE
• Description: IC MCU 64K FLASH 25MHZ 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12E64CFUE

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 2.75 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Package: 80PQFP
• Family Name: HCS12
• Maximum Speed: 25 MHz
• Operating Supply Voltage: 2.5|3.3|5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 60
• Interface Type: SCI/SPI
• On-chip Adc: 16-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 12
• Processor Series: S12E
• Core: HCS12
• Data Ram Size: 4 KB
• Maximum Clock Frequency: 25 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Minimum Operating Temperature: - 40 C
• Controller Family/series: HCS12/S12X
• No. Of I/o's: 58
• Ram Memory Size: 4KB
• Cpu Speed: 25MHz
• No. Of Timers: 4
• Embedded Interface Type: I2C, SCI, SPI
• Rohs Compliant: Yes
• For Use With: M68EVB912E128 - BOARD EVAL FOR MC9S12E128/64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

7.3.2.2
This register is reserved.
Read: always read $00
Write: unimplemented
7.3.2.3
Read: read zeroes when DJM is set
Write: unimplemented when DJM is set
The DAC data register is an 8-bit readable/writable register that stores the data to be converted when DJM
bit is clear. When the DACE bit is set, the value in this register is converted into an analog voltage such
that values from $00 to $FF result in equal voltage increments from V
this register reads zeroes and cannot be written.
Freescale Semiconductor
Module Base + 0x0002
Module Base + 0x0000
Reset
Reset
W
R
W
R
BIT 7
Reserved Register (DACC1)
DAC Data Register — Left Justified (DACD)
0
0
0
7
7
= Unimplemented or Reserved
BIT 6
Figure 7-5. DAC Data Register — Left Justified (DACD)
0
0
0
6
6
Figure 7-4. Reserved Register (DACC1)
BIT 5
MC9S12E128 Data Sheet, Rev. 1.07
0
0
0
5
5
BIT 4
0
0
0
4
4
BIT 3
0
0
0
3
3
Chapter 7 Digital-to-Analog Converter (DAC8B1CV1)
SSA
BIT 2
to V
0
0
0
2
2
REF
. When DJM bit is set,
BIT 1
0
0
0
1
1
BIT 0
0
0
0
0
0
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