HD64F3687GFPV Renesas Electronics America, HD64F3687GFPV Datasheet - Page 291

• Manufacturer Part Number: HD64F3687GFPV
• Description: IC H8 MCU FLASH 56K 64LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H Tinyr

Specifications of HD64F3687GFPV

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 45
• Program Memory Size: 56KB (56K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 64-LQFP
• Package: 64LQFP
• Family Name: H8
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16|32 Bit
• Number Of Programmable I/os: 45
• Interface Type: I2C/SCI
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 3
• For Use With: R0K436079S000BE - KIT DEV FOR H8/36079 W/COMPILER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

15.3.2
PWDRU and PWDRL indicate high level width in one PWM waveform cycle. PWDRU and
PWDRL are 14-bit write-only registers, with the upper 6 bits assigned to PWDRU and the lower 8
bits to PWDRL. When read, all bits are always read as 1.
Both PWDRU and PWDRL are accessible only in bytes. Note that the operation is not guaranteed
if word access is performed. When 14-bit data is written in PWDRU and PWDRL, the contents
are latched in the PWM waveform generator and the PWM waveform generation data is updated.
When writing the 14-bit data, the order is as follows: PWDRL to PWDRU.
PWDRU and PWDRL are initialized to H'C000.
15.4
When using the 14-bit PWM, set the registers in this sequence:
1. Set the PWM bit in the port mode register 1 (PMR1) to set the P11/PWM pin to function as a
2. Set the PWCR0 bit in PWCR to select a conversion period of either.
3. Set the output waveform data in PWDRU and PWDRL. Be sure to write byte data first to
One conversion period consists of 64 pulses, as shown in figure 15.2. The total high-level width
during this period (T
expressed as follows:
where t is the period of PWM clock input: 2/ (bit PWCR0 = 0) or 4/ (bit PWCR0 = 1).
If the data value in PWDRU and PWDRL is from H'FFC0 to H'FFFF, the PWM output stays high.
When the data value is H'C000, T
PWM output pin.
PWDRL and then to PWDRU. When the data is written in PWDRU, the contents of these
registers are latched in the PWM waveform generator, and the PWM waveform generation
data is updated in synchronization with internal signals.
T
T
PWM Data Registers U and L (PWDRU, PWDRL)
Operation
H
H
= (data value in PWDRU and PWDRL + 64) t /2
= 64 t /2 = 32 t
H
) corresponds to the data in PWDRU and PWDRL. This relation can be
H
is calculated as follows:
Rev.5.00 Nov. 02, 2005 Page 257 of 500
Section 15 14-Bit PWM
REJ09B0027-0500