HD64F3687GFPV Renesas Electronics America, HD64F3687GFPV Datasheet - Page 94

• Manufacturer Part Number: HD64F3687GFPV
• Description: IC H8 MCU FLASH 56K 64LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H Tinyr

Specifications of HD64F3687GFPV

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 45
• Program Memory Size: 56KB (56K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 64-LQFP
• Package: 64LQFP
• Family Name: H8
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16|32 Bit
• Number Of Programmable I/os: 45
• Interface Type: I2C/SCI
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 3
• For Use With: R0K436079S000BE - KIT DEV FOR H8/36079 W/COMPILER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 3 Exception Handling
3.4.4
Table 3.2 shows the number of wait states after an interrupt request flag is set until the first
instruction of the interrupt handling-routine is executed.
Table 3.2
Note:
Rev.5.00 Nov. 02, 2005 Page 60 of 500
REJ09B0027-0500
Item
Waiting time for completion of executing instruction*
Saving of PC and CCR to stack
Vector fetch
Instruction fetch
Internal processing
*
SP – 4
SP – 3
SP – 2
SP – 1
SP (R7)
[Legend]
PC H :
PC L :
CCR:
SP:
Notes:
Interrupt Response Time
Not including EEPMOV instruction.
Interrupt Wait States
Upper 8 bits of program counter (PC)
Lower 8 bits of program counter (PC)
Condition code register
Stack pointer
2.
3. Ignored when returning from the interrupt handling routine.
1.
Register contents must always be saved and restored by word length, starting from
an even-numbered address.
PC shows the address of the first instruction to be executed upon return from the interrupt
handling routine.
Prior to start of interrupt
Figure 3.2 Stack Status after Exception Handling
exception handling
Stack area
saved to stack
PC and CCR
SP (R7)
SP + 1
SP + 2
SP + 3
SP + 4
After completion of interrupt
4
States
1 to 23
4
2
4
exception handling
CCR
CCR
PCH
PCL
*3
Even address
Total
15 to 37