M30622SAFP#U5 Renesas Electronics America, M30622SAFP#U5 Datasheet - Page 495

• Manufacturer Part Number: M30622SAFP#U5
• Description: IC M16C MPU ROMLESS 100QFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/60r

Specifications of M30622SAFP#U5

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: SIO, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 50
• Program Memory Type: ROMless
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-QFP
• For Use With: 867-1000 - KIT QUICK START RENESAS 62PM3062PT3-CPE-3 - EMULATOR COMPACT M16C/62P/30P
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

2-176
Power Control
Figure 2.15.3. Memory map of power control-related registers
Figure 2.15.2. Sequence of returning from stop mode
BCLK
Address bus
Data bus
INTi
RD
WR
(5) Sequence of returning from stop mode
Note:
(6) Registers related to power control
Figure 2.15.2 shows the sequence of returning from stop mode.
Sequence of returning from stop mode is oscillation start-up time and interrupt sequence.
When interrupt is generated in stop mode, CM10 becomes “0” and clearing stop mode.
Starting oscillation and supplying BCLK execute the interrupt sequence as follow:
In the interrupt sequence, the processor carries out the following in sequence given:
Figure 2.15.3 shows the memory map of power control-related registers, and Figure 2.15.4 shows
power control-related registers.
Shown above is the case where the main clock is selected for BCLK. If the sub-clock is selected for BCLK,
the sub-clock functions as BCLK when restored from stop mode, with the main clock's divide ratio
unchanged.
(a) CPU gets the interrupt information (the interrupt number and interrupt request level) by read-
(b) Saves the content of the flag register (FLG) as it was immediately before the start of interrupt
(c) Sets the interrupt enable flag (I flag), the debug flag (D flag), and the stack pointer assignment
(d) Saves the content of the temporary register (Note) within the CPU in the stack area.
(e) Saves the content of the program counter (PC) in the stack area.
(f) Sets the interrupt priority level of the accepted instruction in the IPL.
ing address 00000
then be set to “0”.
sequence in the temporary register (Note) within the CPU.
flag (U flag) to “0” (the U flag, however does not change if the INT instruction, in software
interrupt numbers 32 through 63, is executed)
Writing “1” to CM10
(all clock stop control bit)
Stop mode
Note: This register cannot be utilized by the user.
After the interrupt sequence is completed, the processor resumes executing instruc-
tions from the first address of the interrupt routine.
0006
0007
Oscillation start-up
16
16
16
. The interrupt request bit of the interrupt written in address 00000
System clock control register 0 (CM0)
System clock control register 1 (CM1)
Operated by divided-by-8 mode
Address
00000
information
Interrupt
Interrupt sequence approximately 20 cycle (13µ sec)
(Single-chip mode, f(X
Indeterminate
Indeterminate
Indeterminate
IN
) = 16MHz)
SP-2
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
contents
SP-2
SP-4
contents
SP-4
vec
contents
vec
M16C / 62A Group
vec+2
Mitsubishi microcomputers
contents
vec+2
PC
16
will