DF2134AFA20V Renesas Electronics America, DF2134AFA20V Datasheet - Page 1019
DF2134AFA20V
Manufacturer Part Number
DF2134AFA20V
Description
IC H8S/2100 MCU FLASH 80QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheets
1.HEWH8E10A.pdf
(19 pages)
2.D12312SVTE25V.pdf
(341 pages)
3.DF2134AFA20V.pdf
(1063 pages)
Specifications of DF2134AFA20V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
IrDA, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
58
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
80-QFP
For Use With
3DK2166 - DEV EVAL KIT H8S/2166
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2134AFA20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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TCONRS—Timer Connection Register S
Bit
Initial value
Read/Write
TMRX/Y
TMRX/TMRY access select
R/W
0
1
7
0
The TMRX registers are accessed at addresses H'FFF0 to H'FFF5
The TMRY registers are accessed at addresses H'FFF0 to H'FFF5
Internal synchronization signal select
ISGENE
R/W
6
0
Horizontal synchronization output mode select 1 and 0
ISGENE
0
1
HOMOD1
R/W
5
0
HOMOD1 HOMOD0
Vertical synchronization output mode select 1 and 0
ISGENE
0
1
0
1
0
1
HOMOD0
R/W
VOMOD1 VOMOD0
4
0
0
1
0
1
0
1
0
1
0
1
0
1
Clamp waveform mode select 1 and 0
ISGENE
VOMOD1
0
1
The IHI signal (without 2fH modification) is selected
The IHI signal (with 2fH modification) is selected
The CLI signal is selected
The IHG signal is selected
Rev. 4.00 Jun 06, 2006 page 963 of 1004
R/W
H'FFFE
3
0
0
1
0
1
0
1
0
1
CLMOD1 CLMOD0
0
1
0
1
The IVI signal (without fall modification
or IHI synchronization) is selected
The IVI signal (without fall modification,
with IHI synchronization) is selected
The IVI signal (with fall modification,
without IHI synchronization) is selected
The IVI signal (with fall modification and
IHI synchronization) is selected
The IVG signal is selected
VOMOD0
Appendix B Internal I/O Registers
R/W
2
0
0
1
0
1
0
1
0
1
Description
CLMOD1
The CL1 signal is selected
The CL2 signal is selected
The CL3 signal is selected
The CL4 signal is selected
Description
R/W
1
0
Timer Connection
Description
REJ09B0301-0400
CLMOD0
R/W
0
0
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