DF2134AFA20V Renesas Electronics America, DF2134AFA20V Datasheet - Page 451
DF2134AFA20V
Manufacturer Part Number
DF2134AFA20V
Description
IC H8S/2100 MCU FLASH 80QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheets
1.HEWH8E10A.pdf
(19 pages)
2.D12312SVTE25V.pdf
(341 pages)
3.DF2134AFA20V.pdf
(1063 pages)
Specifications of DF2134AFA20V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
IrDA, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
58
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
80-QFP
For Use With
3DK2166 - DEV EVAL KIT H8S/2166
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2134AFA20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Bit 5—Parity Enable (PE): In asynchronous mode, selects whether or not parity bit addition is
performed in transmission, and parity bit checking in reception. In synchronous mode, or when a
multiprocessor format is used, parity bit addition and checking is not performed, regardless of the
PE bit setting.
Note:
Bit 4—Parity Mode (O/E E E E ): Selects either even or odd parity for use in parity addition and
checking.
The O/E bit setting is only valid when the PE bit is set to 1, enabling parity bit addition and
checking, in asynchronous mode. The O/E bit setting is invalid in synchronous mode, when parity
bit addition and checking is disabled in asynchronous mode, and when a multiprocessor format is
used.
Notes: 1. When even parity is set, parity bit addition is performed in transmission so that the total
Bit 5
PE
0
1
Bit 4
O/E E E E
0
1
* When the PE bit is set to 1, the parity (even or odd) specified by the O/E bit is added to
2. When odd parity is set, parity bit addition is performed in transmission so that the total
transmit data before transmission. In reception, the parity bit is checked for the parity
(even or odd) specified by the O/E bit.
number of 1 bits in the transmit character plus the parity bit is even.
In reception, a check is performed to see if the total number of 1 bits in the receive
character plus the parity bit is even.
number of 1 bits in the transmit character plus the parity bit is odd.
In reception, a check is performed to see if the total number of 1 bits in the receive
character plus the parity bit is odd.
Description
Parity bit addition and checking disabled
Parity bit addition and checking enabled *
Description
Even parity *
Odd parity *
2
1
Section 15 Serial Communication Interface (SCI, IrDA)
Rev. 4.00 Jun 06, 2006 page 395 of 1004
REJ09B0301-0400
(Initial value)
(Initial value)
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