DF2134AFA20V Renesas Electronics America, DF2134AFA20V Datasheet - Page 401
DF2134AFA20V
Manufacturer Part Number
DF2134AFA20V
Description
IC H8S/2100 MCU FLASH 80QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheets
1.HEWH8E10A.pdf
(19 pages)
2.D12312SVTE25V.pdf
(341 pages)
3.DF2134AFA20V.pdf
(1063 pages)
Specifications of DF2134AFA20V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
IrDA, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
58
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
80-QFP
For Use With
3DK2166 - DEV EVAL KIT H8S/2166
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Price
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Part Number:
DF2134AFA20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Bits 7 and 6—Input Synchronization Mode Select 1 and 0 (SIMOD1, SIMOD0): These bits
select the signal source of the IHI and IVI signals.
Bit 5—Synchronization Signal Connection Enable (SCONE): Selects the signal source of the
FRT FTI input and the TMR1 TMCI1/TMRI1 input.
Bit 4—Input Capture Start Bit (ICST): The TMRX external reset input (TMRIX) is connected
to the IHI signal. TMRX has input capture registers (TICR, TICRR, and TICRF). TICRR and
TICRF can measure the width of a short pulse by means of a single capture operation under the
control of the ICST bit. When a rising edge followed by a falling edge is detected on TMRIX after
the ICST bit is set to 1, the contents of TCNT at those points are captured into TICRR and TICRF,
respectively, and the ICST bit is cleared to 0.
Bit 7
SIMOD1
0
1
Bit 5
SCONE
0
1
Bit 4
ICST
0
1
Mode
Normal connection
Synchronization signal
connection mode
Bit 6
SIMOD0
0
1
0
1
Description
The TICRR and TICRF input capture functions are stopped
[Clearing condition]
When a rising edge followed by a falling edge is detected on TMRIX
The TICRR and TICRF input capture functions are operating
(Waiting for detection of a rising edge followed by a falling edge on TMRIX)
[Setting condition]
When 1 is written in ICST after reading ICST = 0
(Initial value)
Mode
No signal
S-on-G mode
Composite mode
Separate mode
(Initial value)
FTIA
input
IVI
signal
FTIA
Description
Section 13 Timer Connection [H8S/2138 Group]
FTIB
FTIB
input
TMO1
signal
Rev. 4.00 Jun 06, 2006 page 345 of 1004
Description
HFBACKI input
HSYNCI input
IHI Signal
CSYNCI input
HSYNCI input
FTIC
FTIC
input
VFBACKI
input
FTID
FTID
input
IHI
signal
VFBACKI input
IVI Signal
PDC input
PDC input
VSYNCI input
TMCI1
TMCI1
input
IHI
signal
REJ09B0301-0400
(Initial value)
TMRI1
TMRI1
input
IVI
inverse
signal
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