DF2134AFA20V Renesas Electronics America, DF2134AFA20V Datasheet - Page 918
DF2134AFA20V
Manufacturer Part Number
DF2134AFA20V
Description
IC H8S/2100 MCU FLASH 80QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheets
1.HEWH8E10A.pdf
(19 pages)
2.D12312SVTE25V.pdf
(341 pages)
3.DF2134AFA20V.pdf
(1063 pages)
Specifications of DF2134AFA20V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
IrDA, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
58
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
80-QFP
For Use With
3DK2166 - DEV EVAL KIT H8S/2166
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2134AFA20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Appendix A Instruction Set
A.5
Table A.6 indicates the types of cycles that occur during instruction execution by the CPU. See
table A.4 for the number of states per cycle.
How to Read the Table:
Legend:
R:B
R:W
W:B
W:W
:M
2nd
3rd
4th
5th
NEXT
EA
VEC
Rev. 4.00 Jun 06, 2006 page 862 of 1004
REJ09B0301-0400
JMP@aa:24
Instruction
Bus States during Instruction Execution
R:W 2nd
Byte-size read
Word-size read
Byte-size write
Word-size write
Transfer of the bus is not performed immediately after this cycle
Address of 2nd word (3rd and 4th bytes)
Address of 3rd word (5th and 6th bytes)
Address of 4th word (7th and 8th bytes)
Address of 5th word (9th and 10th bytes)
Start address of instruction following executing instruction
Effective address
Vector address
1
Internal
operation,
2 state
2
R:W EA
3
4
Order of execution
End of instruction
Read effective address (word-size read)
No read or write
Read 2nd word of current instruction
(word-size read)
5
6
7
8
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