MC9S12HZ128CAL Freescale Semiconductor, MC9S12HZ128CAL Datasheet - Page 158

• Manufacturer Part Number: MC9S12HZ128CAL
• Description: IC MCU 16BIT 128K FLASH 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12HZ128CAL

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: CAN, EBI/EMI, I²C, SCI, SPI
• Peripherals: LCD, Motor control PWM, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: S12H
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 6 KB
• Interface Type: I2C, SCI, SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 85
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 4 Port Integration Module (PIM9HZ256V2)
4.3.8.4
Read: anytime. Write: Anytime.
This register enables the slew rate control and disables the digital input buffer for port pins PV[7:0].
4.3.8.5
Read: Anytime. Write: Anytime.
This register configures whether a pull-up or a pull-down device is activated on configured input pins. If
a pin is configured as output, the corresponding Pull Device Enable Register bit has no effect.
158
SRRV[7:0]
PERV[7:0]
Reset
Reset
Field
Field
7:0
7:0
W
W
R
R
SRRV7
PERV7
Slew Rate Port V
0 Disables slew rate control and enables digital input buffer.
1 Enables slew rate control and disables digital input buffer.
Pull Device Enable Port V
0 Pull-up or pull-down device is disabled.
1 Pull-up or pull-down device is enabled.
Port V Slew Rate Register (SRRV)
Port V Pull Device Enable Register (PERV)
0
0
7
7
SRRV6
PERV6
Figure 4-53. Port V Pull Device Enable Register (PERV)
0
0
6
6
Figure 4-52. Port V Slew Rate Register (SRRV)
Table 4-37. SRRV Field Descriptions
Table 4-38. PERV Field Descriptions
SRRV5
PERV5
MC9S12HZ256 Data Sheet, Rev. 2.05
0
0
5
5
SRRV4
PERV4
0
0
4
4
Description
Description
SRRV3
PERV3
0
0
3
3
SRRV2
PERV2
0
0
2
2
SRRV1
PERV1
Freescale Semiconductor
0
0
1
1
SRRV0
PERV0
0
0
0
0