MC9S12HZ128CAL Freescale Semiconductor, MC9S12HZ128CAL Datasheet - Page 558

• Manufacturer Part Number: MC9S12HZ128CAL
• Description: IC MCU 16BIT 128K FLASH 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12HZ128CAL

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: CAN, EBI/EMI, I²C, SCI, SPI
• Peripherals: LCD, Motor control PWM, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 6K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: S12H
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 6 KB
• Interface Type: I2C, SCI, SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 85
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 19 Debug Module (DBGV1)
control (TBC) block. When PAGSEL = 01, registers DBGCAX, DBGCBX, and DBGCCX are used to
match the upper addresses as shown in
19.4.2.1.1
Read or write comparisons are useful only with TRGSEL = 0, because only opcodes should be tagged as
they are “read” from memory. RWAEN and RWBEN are ignored when TRGSEL = 1.
In full modes (“A and B” and “A and not B”) RWAEN and RWA are used to select read or write
comparisons for both comparators A and B.
the DBGCB comparison conditions. The RWBEN and RWB bits are not used and are ignored in full
modes.
19.4.2.1.2
The TRGSEL bit in DBGC1 is used to determine the triggering condition in DBG mode. TRGSEL applies
to both trigger A and B except in the event only trigger modes. By setting TRGSEL, the comparators A
and B will qualify a match with the output of opcode tracking logic and a trigger occurs before the tagged
instruction executes (tagged-type trigger). With the TRGSEL bit cleared, a comparator match forces a
trigger when the matching condition occurs (force-type trigger).
19.4.2.2
The TBC is the main controller for the DBG module. Its function is to decide whether data should be stored
in the trace buffer based on the trigger mode and the match signals from the comparator. The TBC also
determines whether a request to break the CPU should occur.
558
Trace Buffer Control (TBC)
RWAEN bit
If a tagged-type C breakpoint is set at the same address as an A/B
tagged-type trigger (including the initial entry in an inside or outside range
trigger), the C breakpoint will have priority and the trigger will not be
recognized.
Read or Write Comparison
Trigger Selection
If the TRGSEL is set, the address stored in the comparator match address
registers must be an opcode address for the trigger to occur.
0
0
1
1
1
1
Table 19-24. Read or Write Comparison Logic Table
RWA bit
x
x
0
0
1
1
MC9S12HZ256 Data Sheet, Rev. 2.05
Table
Table 19-24
RW signal
19-11.
0
1
0
1
0
1
NOTE
NOTE
shows the effect for RWAEN, RWA, and RW on
No data bus compare since RW=1
No data bus compare since RW=0
Write data bus
Read data bus
Write data bus
Read data bus
Comment
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