ADUC7128BSTZ126-RL Analog Devices Inc, ADUC7128BSTZ126-RL Datasheet - Page 49

• Manufacturer Part Number: ADUC7128BSTZ126-RL
• Description: IC DAS MCU ARM7 ADC/DDS 64-LQFP
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7128BSTZ126-RL

• Core Size: 16/32-Bit
• Program Memory Size: 126KB (126K x 8)
• Core Processor: ARM7
• Speed: 41.78MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: PLA, POR, PWM, PSM, Temp Sensor, WDT
• Number Of I /o: 28
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x12b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 64-LQFP
• Controller Family/series: (ARM7) ADUC
• No. Of I/o's: 40
• Cpu Speed: 41.78MHz
• No. Of Timers: 5
• Digital Ic Case Style: LQFP
• Embedded Interface Type: I2C, SPI, UART
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-ADUC7128QSPZ - KIT DEV FOR ADUC7128
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: ADUC7128BSTZ126-RLTR

OSCILLATOR AND PLL—POWER CONTROL
The ADuC7128/ADuC7129 integrate a 32.768 kHz oscillator,
a clock divider, and a PLL. The PLL locks onto a multiple (1275)
of the internal oscillator to provide a stable 41.78 MHz clock for
the system. The core can operate at this frequency, or at binary
submultiples of it, to allow power saving. The default core clock
is the PLL clock divided by 8 (CD = 3) or 5.2 MHz. The core
clock frequency can be output on the ECLK pin as described in
Figure 48. Note that when the ECLK pin is used to output the
core clock, the output signal is not buffered and is not suitable
for use as a clock source to an external device without an
external buffer.
A power-down mode is available on the ADuC7128/ADuC7129.
The operating mode, clocking mode, and programmable clock
divider are controlled via two MMRs, PLLCON (see Table 61) and
POWCON (see Table 62). PLLCON controls operating mode of
the clock system, and POWCON controls the core clock
frequency and the power-down mode.
External Crystal Selection
To switch to an external crystal, use the following procedure:
1.
2.
3.
4.
WATCHDOG
1
32.768kHz ±3%
WAKEUP
TIMER
TIMER
Enable the Timer2 interrupt and configure it for a timeout
period of >120 μs.
Follow the write sequence to the PLLCON register, setting
the MDCLK bits to 01 and clearing the OSEL bit.
Force the part into nap mode by following the correct write
sequence to the POWCON register.
When the part is interrupted from nap mode by the Timer2
interrupt source, the clock source has switched to the
external clock.
CORE
OSCILLATOR
INT. 32kHz
OCLK 32.768kHz
Figure 48. Clocking System
PLL
I
2
C
1
CD
40.78MHz
UCLK
OSCILLATOR
AT POWER UP
P0.7/ECLK
CRYSTAL
/2
CD
HCLK
PERIPHERALS
MDCLK
ANALOG
XCLKO
XCLKI
P0.7/XCLK
Rev. 0 | Page 49 of 92
Example Source Code
3)) //ensures timer value loaded
//enable T2 interrupt
// Set Core into Nap mode
In noisy environments, noise can couple to the external crystal
pins, and PLL may lose lock momentarily. A PLL interrupt is
provided in the interrupt controller. The core clock is immediately
halted, and this interrupt is serviced only when the lock is restored.
In case of crystal loss, the watchdog timer should be used. During
initialization, a test on the RSTSTA can determine if the reset
came from the watchdog timer.
External Clock Selection
To switch to an external clock on P0.7, configure P0.7 in
Mode 1. The external clock can be up to 44 MHz, providing
the tolerance is 1%.
Example Source Code
3)) //ensures timer value loaded
//enable T2 interrupt
Power Control System
A choice of operating modes is available on the ADuC7128/
ADuC7129. Table 58 describes what part of the ADuC7128/
ADuC7129 is powered on in the different modes and indicates
the power-up time. Table 59 gives some typical values of the total
current consumption (analog + digital supply currents) in the
different modes, depending on the clock divider bits. The ADC is
turned off.
Note that these values also include current consumption of the
regulator and other parts on the test board on which these values
were measured.
T2LD = 5;
TCON = 0x480;
while ((T2VAL == t2val_old) || (T2VAL >
IRQEN = 0x10;
PLLKEY1 = 0xAA;
PLLCON = 0x01;
PLLKEY2 = 0x55;
POWKEY1 = 0x01;
POWCON = 0x27;
POWKEY2 = 0xF4;
while ((T2VAL == t2val_old) || (T2VAL >
IRQEN = 0x10;
PLLKEY1 = 0xAA;
PLLCON = 0x03; //Select external clock
PLLKEY2 = 0x55;
POWKEY1 = 0x01;
POWCON = 0x27; // Set Core into Nap mode
POWKEY2 = 0xF4;
T2LD = 5;
TCON = 0x480;
ADuC7128/ADuC7129