ADUC7128BSTZ126-RL Analog Devices Inc, ADUC7128BSTZ126-RL Datasheet - Page 87

• Manufacturer Part Number: ADUC7128BSTZ126-RL
• Description: IC DAS MCU ARM7 ADC/DDS 64-LQFP
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7128BSTZ126-RL

• Core Size: 16/32-Bit
• Program Memory Size: 126KB (126K x 8)
• Core Processor: ARM7
• Speed: 41.78MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: PLA, POR, PWM, PSM, Temp Sensor, WDT
• Number Of I /o: 28
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x12b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 64-LQFP
• Controller Family/series: (ARM7) ADUC
• No. Of I/o's: 40
• Cpu Speed: 41.78MHz
• No. Of Timers: 5
• Digital Ic Case Style: LQFP
• Embedded Interface Type: I2C, SPI, UART
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-ADUC7128QSPZ - KIT DEV FOR ADUC7128
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: ADUC7128BSTZ126-RLTR

HARDWARE DESIGN CONSIDERATIONS
POWER SUPPLIES
The ADuC7128/ADuC7129 operational power supply voltage
range is 3.0 V to 3.6 V. Separate analog and digital power supply
pins (AV
relatively free of noisy digital signals often present on the system
IOV
supplies, that is, using different voltage supply levels for each
supply. For example, the system can be designed to operate with
an IOV
3 V, or vice versa, if required. A typical split supply configuration
is shown in Figure 66.
As an alternative to providing two separate power supplies, the
user can help keep AV
and/or ferrite bead between AV
AV
shown in Figure 67. With this configuration, other analog circuitry
(such as op amps or voltage references) can be powered from
the AV
Note that in both Figure 66 and Figure 67, a large value (10 μF)
reservoir capacitor sits on IOV
sits on AV
are located at each AV
standard design practice, be sure to include all of these capaci-
tors and ensure that the smaller capacitors are close to each
AV
DD
DD
DD
DIGITAL SUPPLY
DIGITAL SUPPLY
0.1µF
0.1µF
separately to ground. An example of this configuration is
pin with trace lengths as short as possible.
line. In this mode, the part can also operate with split
DD
DD
DD
0.47µF
0.47µF
supply line as well.
voltage level of 3.3 V while the AV
DD
+
and IOV
10µF
. In addition, local small value (0.1 μF) capacitors
Figure 67. External Single Supply Connections
Figure 66. External Dual Supply Connections
+
10µF
DD
DD
DD
, respectively) allow AV
and IOV
quiet by placing a small series resistor
BEAD
IOV
LV
PV
DACV
IOGND
IOV
LV
PV
DACV
IOGND
ADuC7128
ADuC7128
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DACGND
DACGND
REFGND
REFGND
GND
GND
and IOV
AGND
AGND
and a separate 10 μF capacitor
DD
AV
AV
REF
REF
DD
DD
pin of the chip. As per
1.6V
DD
10µF
ANALOG SUPPLY
, and then decoupling
DD
10µF
0.1µF
0.1µF
DD
level can be at
+
to be kept
+
0.1µF
0.1µF
Rev. 0 | Page 87 of 92
Connect the ground terminal of each of these capacitors directly
to the underlying ground plane. It should also be noted that, at
all times, the analog and digital ground pins on the ADuC7128/
ADuC7129 must be referenced to the same system ground refer-
ence point.
Finally, on the LFCSP package, the paddle on the bottom of the
package should be soldered to a metal plate to provide mechanical
stability. The metal plate should be connected to ground.
Linear Voltage Regulator
The ADuC7128/ADuC7129 require a single 3.3 V supply, but
the core logic requires a 2.5 V supply. An on-chip linear regulator
generates the 2.5 V from IOV
is the 2.5 V supply for the core logic. The DAC logic and PLL logic
also require a 2.5 V supply that must be connected externally from
the LV
compensation capacitor of 0.47 μF must be connected between
LV
tank of charge, as shown in Figure 68. In addition, decoupling
capacitors of 0.1 μF must be placed as close as possible to the
PV
The LV
recommended that the IOV
decoupling to help improve line regulation performance of the
on-chip voltage regulator.
GROUNDING AND BOARD LAYOUT
RECOMMENDATIONS
As with all high resolution data converters, special attention
must be paid to grounding and PC board layout of the design to
achieve optimum performance from the ADCs and DAC.
Although the ADuC7128/ADuC7129 have separate pins for
analog and digital ground (AGND and IOGND), the user must
not tie these to two separate ground planes unless the two ground
planes are connected together very close to the ADuC7128/
ADuC7129, as illustrated in the simplified example of Figure 69a.
In systems where digital and analog ground planes are connected
together somewhere else (for example, at the system power
supply), they cannot be connected again near the ADuC7128/
ADuC7129 because a ground loop results.
DD
DD
and DGND (as close as possible to these pins) to act as a
pin and the DACV
DD
DD
pin to the DACV
pin should not be used for any other chip. It is also
0.47µF
Figure 68. Voltage Regulator Connections
0.1µF
DD
DD
pin.
pin and the PV
DD
DD
ADuC7128/ADuC7129
have excellent power supply
for the core logic. The LV
LV
PV
DACV
ADuC7128
DD
DD
DD
DD
pin. An external
DD
pin