ADUC7128BSTZ126-RL Analog Devices Inc, ADUC7128BSTZ126-RL Datasheet - Page 73

• Manufacturer Part Number: ADUC7128BSTZ126-RL
• Description: IC DAS MCU ARM7 ADC/DDS 64-LQFP
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7128BSTZ126-RL

• Core Size: 16/32-Bit
• Program Memory Size: 126KB (126K x 8)
• Core Processor: ARM7
• Speed: 41.78MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: PLA, POR, PWM, PSM, Temp Sensor, WDT
• Number Of I /o: 28
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x12b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 64-LQFP
• Controller Family/series: (ARM7) ADUC
• No. Of I/o's: 40
• Cpu Speed: 41.78MHz
• No. Of Timers: 5
• Digital Ic Case Style: LQFP
• Embedded Interface Type: I2C, SPI, UART
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-ADUC7128QSPZ - KIT DEV FOR ADUC7128
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: ADUC7128BSTZ126-RLTR

Programmed Interrupts
As the programmed interrupts are nonmaskable, they are
controlled by the SWICFG register that writes into both the
IRQSTA and IRQSIG registers and/or FIQSTA and FIQSIG
registers at the same time. The 32-bit register dedicated to
software interrupt is SWICFG described in Table 106. This
MMR allows the control of programmed source interrupt.
Table 106. SWICFG MMR Bit Designations
Bit
31:3
2
1
0
Note that any interrupt signal must be active for at least the
equivalent of the interrupt latency time, to be detected by the
interrupt controller and to be detected by the user in the
IRQSTA/FIQSTA register.
TIMERS
The ADuC7128/ADuC7129 have five general purpose
timers/counters.
•
•
•
•
•
The five timers in their normal mode of operation can be either
free-running or periodic.
In free-running mode, the counter decrements or increments
from the maximum or minimum value until zero scale or full
scale and starts again at the maximum or minimum value.
In periodic mode, the counter decrements/increments from the
value in the load register (TxLD MMR) until zero scale or full
scale and starts again at the value stored in the load register.
The value of a counter can be read at any time by accessing its
value register (TxVAL). Timers are started by writing in the
control register of the corresponding timer (TxCON).
Timer0
Timer1
Timer2 or wake-up timer
Timer3 or watchdog timer
Timer4
Description
Reserved.
Programmed Interrupt (FIQ). Setting/clearing this bit
corresponds to setting/clearing Bit 1 of FIQSTA and
FIQSIG.
Programmed Interrupt (IRQ). Setting/clearing this bit
corresponds to setting/clearing Bit 1 of IRQSTA and
IRQSIG.
Reserved.
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In normal mode, an IRQ is generated each time the value of the
counter reaches zero, if counting down; or full scale, if counting
up. An IRQ can be cleared by writing any value to clear the register
of the particular timer (TxICLR).
Table 107. Event Selection Numbers
ES
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
TIMER0—LIFETIME TIMER
Timer0 is a general-purpose, 48-bit count up, or a 16-bit count
up/down timer with a programmable prescaler. Timer0 is
clocked from the core clock, with a prescaler of 1, 16, 256, or
32,768. This gives a minimum resolution of 22 ns when the core
is operating at 41.78 MHz and with a prescaler of 1.
In 48-bit mode, Timer0 counts up from zero. The current
counter value can be read from T0VAL0 and T0VAL1.
In 16-bit mode, Timer0 can count up or count down. A 16-bit
value can be written to T0LD, which is loaded into the counter.
The current counter value can be read from T0VAL0. Timer0 has
a capture register (T0CAP) that can be triggered by a selected IRQ
source initial assertion. Once triggered, the current timer value is
copied to T0CAP, and the timer keeps running. This feature can be
used to determine the assertion of an event with more accuracy
than by servicing an interrupt alone.
Timer0 reloads the value from T0LD either when TIMER0
overflows or immediately when T0ICLR is written.
Interrupt Number
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
ADuC7128/ADuC7129
Name
RTOS Timer (Timer0)
GP Timer0 (Timer1)
Wake-Up Timer (Timer2)
Watchdog Timer (Timer3)
GP Timer1 (Timer4)
Flash Control 0
Flash Control 1
ADC Channel
Quadrature Encoder
I2C Slave0
I2C Slave1
I2C Master0
I2C Master1
SPI Slave
SPI Master
UART0
UART1
External IRQ0